Time shift circuit for functional and AC parametric test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S744000

Reexamination Certificate

active

06934896

ABSTRACT:
A time shift circuit for changing a delay timing of a portion of a test pattern for testing a semiconductor device. The time shift circuit includes a multiplexer for selectively producing delay value data indicating a value of time shift in response to a shift command signal, a vernier delay unit for producing timing vernier data based on the delay value data selected by the multiplexer, and a timing generator for generating a timing edge for the specific portion of the test pattern based on the timing vernier data from the vernier delay unit. The shift command signal sets either a normal mode where predetermined delay value data is selected by the multiplexer or a time shift mode where delay value data for shifting the timing edge in real time is selected by the multiplexer.

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patent: 6263463 (2001-07-01), Hashimoto
patent: 6457148 (2002-09-01), Yoshiba
patent: 6532561 (2003-03-01), Turnquist et al.

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