Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-04
2001-10-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000
Reexamination Certificate
active
06309926
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to photo-lithography, and more particularly relates to a method of forming sub-micron gates using short wavelength radiation and ultra-thin photoresists.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and size of memory cells, and surface geometry of various features such as corners and edges.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the photoresist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The photoresist receives a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the photoresist. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the photoresist through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the photoresist as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. As feature sizes are driven smaller and smaller, optical systems are approaching their limits caused by the wavelengths of the optical radiation. A recognized way of reducing the feature size of circuit elements is to lithographically image the features with radiation of a shorter wavelength. “Long” or “soft” x-rays (extreme ultraviolet (EUV), deep ultraviolet (DUV)), wavelength range of 5-200 nm are now at the forefront of research in an effort to achieve the smaller desired feature sizes.
Although EUV lithography provides substantial advantages with respect to achieving high resolution patterning, the shorter wavelength radiation is highly absorbed by the photoresist material. Consequently, the penetration depth of the radiation into the photoresist is limited. The limited penetration depth of the shorter wavelength radiation requires the use of ultra-thin photoresists so that the radiation can penetrate the entire depth of the photoresist in order to effect patterning thereof. However, the thinness of such ultra-thin photoresists results in the etch resistance thereof being relatively low. In other words, the etch protection afforded by ultra-thin photoresists is limited which in turn limits the EUV lithographic process.
SUMMARY OF THE INVENTION
The present invention relates to a method to facilitate lithographic processes employing extreme ultra-violet (EUV) radiation and/or deep UV radiation in fabricating gates. As noted above, EUV and deep UV radiation are preferred radiation sources in lithographic processes where fine resolution is desired. The short wavelengths of these types of radiation afford for fine patterning (e.g., critical feature sizes <0.25 &mgr;m). However, these types of radiation are highly absorbed by photoresist material which consequently limits the depth of penetration by the radiation into the photoresist material.
By employing a nitride layer to be patterned as a hard mask for use in connection with etching the gates, the present invention affords for expanding available etch chemistries useable in EUV and/or deep UV lithographic processes. In particular, these types of lithographic processes require the use of very thin photoresists as a result of the depth of penetration limitations of the short wavelength radiation. Such very thin photoresists are limited in their capacity as etch barriers due to the thickness thereof.
In the present invention, the ultra-thin photoresist is employed in patterning and etching the nitride thereunder to form a hard mask. A gate pattern formed in the photoresist with the short wavelength radiation is transferred to the nitride layer by a first etch step. The patterned nitride layer is used as a hard mask for a subsequent second etch step to etch a gate material layer (e.g., polysilicon or metal) so as to form a gate corresponding to the gate pattern. This methodology is used in conjunction with fabrication steps employed in making the particular device(s) (e.g., memory cells, analog devices) using the gate. Thus, the present invention affords for taking advantage of the fine resolution patterning available from EUV and deep UV lithographic processes and mitigates the limitations associated therewith with respect to etch chemistry.
One specific aspect of the present invention relates to a method of forming a gate structure. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the gate. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the gate pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer. The nitride layer is used as a hard mask during a second etch step to form the gate by transferring the gate pattern to the gate material layer via the second etch step.
Another specific aspect of the present invention relates to a memory cell structure including a plurality of memory cells, each of the memory cells including a floating gate, at least two of the floating gates being separated by a distance below about 0.18 &mgr;m. In forming the memory cell structure a first nitride layer is formed on a first gate material layer. A first ultra-thin photoresist layer is formed on the first nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the floating gates. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the floating gate pattern to the first nitride layer. The first etch step includes an etch chemistry that is selective to the first nitride layer over the first ultra-thin photoresist layer. The first nitride layer is used as a hard mask during a second etch step to form the floating gates by transferring the floating gate pattern to the first gate material layer via the second etch step. An interpoly dielectric layer is formed over the floating gates. A second gate material layer is formed over the interpoly dielectric layer. A second nitride layer is formed on the second gate material layer. A second ultra-thin photoresist layer is formed on the second nitride layer. The second ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for control gates. The second ultra-thin photoresist layer is used as a mask during a third etch step to transfer the control gate pattern to the second nitride layer. The third etch step includes an etch chemistry that is selective to the second nitride layer over the second ultra-thin photoresist layer. The second nitride layer is used as a hard mask during a fourth etch step to form the control gates by transferring the control gate pattern to the second gate material layer via the fourth etch step.
Still another aspect of the present invention relates to a method of forming a gate. A nitride layer is formed on a gate material layer, the nitride layer having a thickness within the range of 50 Å-200
Bell Scott A.
Levinson Harry J.
Lyons Christopher F.
Nguyen Khanh B.
Wang Fei
Advanced Micro Devices
Amin & Turocy LLP
Kennedy Jennifer M.
Niebling John F.
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