Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1995-06-07
2002-09-03
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C174S261000
Reexamination Certificate
active
06444919
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to wiring systems for multi-chip modules and, more particularly, to wiring systems which facilitate repair and engineering changes in multi-chip modules fabricated from a plurality of layers, such as multi-layer ceramic modules and module wiring formed by thin film techniques.
A demand for increased complexity of electronic systems including integrated circuit chips has caused the development of the multi-chip module (MCM) which includes a plurality of integrated circuit chips.
Such MCMs usually take the form of relatively large, multi-layer constructions having a surface on which a plurality of chips may be mounted. Wiring can be run in a direction parallel to the surface at the interface between any two layers. Wiring can also be run perpendicular to the surface and between wiring layers with through-holes or vias in the layers which are filled with conductive material. MCMs have been implemented with a variety of technologies including multi-layered co-fired ceramics, silicon based thin film structures, ceramic based thin film structures and combinations of those techniques.
However, because of the multi-layer construction, there is no access to wiring other than on the surface of the multi-layer structure. Therefore, engineering changes or wiring repairs cannot readily be made.
Since such structures are complex and require a number of processing steps for each layer, substantial expense is involved in the fabrication of the multi-layer structure. It is therefore economically important that engineering changes be possible and that the multi-layer structure be repairable. In the past, engineering changes and/or repairs have been accomplished by providing one or more layers of redistribution wiring from the chip input/output (I/O) pads to engineering change (EC) pads on the top surface of the multi-layer structure. As shown in Chance et al. U.S. Pat. No. 4,489,364, the disclosure of which is incorporated by reference herein, an electronic circuit module in which connections to pads to which chips are connected are buried within the body of the multi-layer structure but are periodically brought to the surface of the module and linked by EC pads of a so-called “dog-bone” shape. Continuity of these connections may be broken by severing the narrow portion of the dog bone. The EC or repair is made by wiring from EC pad to EC pad using a so-called “yellow wire” (which bypasses the severed dog bone) and by redistribution wiring formed in the multi-layer structure from EC pad to chip I/O pad.
Ho U.S. Pat. No. 4,254,445, the disclosure of which is incorporated by reference herein, discloses an alternative wiring scheme wherein engineering change interconnection lines are placed parallel to chip sites and terminate at pads adjacent to the chip site. Fly wires are used to connect the desired engineering change interconnection lines at crossover points or to connect an engineering change interconnection line to an EC pad at a chip site.
More recently, Bhatia et al. U.S. Pat. No. 5,243,140, the disclosure of which is incorporated by reference herein, discloses an engineering change wiring scheme wherein wiring changes at the chip site may be made using surface wiring but changes between chip sites must still be made using buried EC wires and their accompanying EC pads.
Weigler et al. U.S. Pat. Nos. 5,220,490 and 5,224,022 disclose subsurface wiring channels which are interspersed among the chip sites. Wiring changes may be made through the use of “spot links” on the surface of the substrate.
What all the above prior art solutions have in common is the need for buried wiring and EC pads to accomplish their EC and repair functions. It would be desirable to be able to accomplish ECs and wiring repairs without the need for buried wiring and EC pads.
Thus, it is a purpose of the present invention to have a wiring scheme to accomplish ECs and wiring repairs without the necessity of having buried EC wiring and EC pads.
It is another purpose of the present invention to have a wiring scheme that is substantially on the surface of the substrate.
It is yet another purpose of the present invention to have a wiring scheme that is flexible in nature so as to easily allow ECs and wiring repairs.
These and other purposes of the present invention will become more apparent after referring to the following description of the invention in conjunction with the accompanying drawings.
BRIEF SUMMARY OF THE INVENTION
One aspect of the invention relates to a thin film layer wiring scheme on a substrate comprising:
at least two chip connection pads at a first chip site on the thin film layer:
a first directional wiring line interspersed between the first chip site chip connection pads;
at least one wiring interconnection line connecting one first chip site chip connection pad with the first directional wiring line at the first chip site;
at least two chip connection pads at a second chip site on the thin film layer;
a first directional wiring line interspersed between the second chip site chip connection pads; and
at least one chip site interconnection line connecting the first directional wiring line at the first chip site with the first directional wiring line at the second chip site.
A second aspect of the invention relates to a thin film layer wiring scheme on a substrate comprising:
a plurality of chip connection pads at a first chip site on the thin film layer;
a plurality of directional wiring lines interspersed between the first chip site chip connection pads, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines;
at least one wiring interconnection line connecting one first chip site chip connection pad with one of the directional wiring lines at the first chip site;
a plurality of chip connection pads at a second chip site on the thin film layer;
a plurality of directional wiring lines interspersed between the second chip site chip connection pads, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines;
at least one wiring interconnection line connecting one second chip site chip connection pad with one of the directional wiring lines at the second chip site; and
a plurality of chip site interconnection lines connecting at least one of the directional wiring lines at the first chip site with at least one of the directional wiring lines at the second chip site.
A third aspect of the invention relates to a method of modifying a thin film layer wiring scheme on a substrate comprising a plurality of chip connection pads at each of a first chip site on the substrate and a second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines, the method comprising the steps of:
depositing metallization so as to form a wiring interconnection line connecting one chip connection pad at the first chip site to a directional wiring line at the first chip site;
deleting a portion of at least one of the directional wiring lines at the first chip site;
depositing metallization so as to form a wiring interconnection line connecting one chip connection pad at the second chip site to a directional wiring line at the second chip site;
deleting a portion of at least one of the directional wiring lines at the second chip site; and
connecting the directional wiring line at the first chip site to the directional wiring line at the second chip site by a chip site interconnection line.
REFERENCES:
patent: 3371250 (1968-02-01), Ross et al.
patent: 4254445 (1981-03-01), Ho
patent: 4489364 (1984-12-01), Chance et al.
patent: 5220490 (1993-06-01), Weigler et al.
patent: 5224022 (1993-06-01), Weigler et al.
patent: 5243140 (1993-09-01), Bhatia
Economikos Laertis
Farooq Mukta Shaji
McAllister Michael Ford
Perfecto Eric Daniel
Prasad Chandrika
Blecker Ira D.
Cuneo Kamand
International Business Machines - Corporation
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