Thick oxide MOS device used in ESD protection circuit

Details Thick oxide MOS device used in ESD protection circuit Thick oxide MOS device used in ESD protection circuit

1999-11-05

2001-12-11

Bowers, Charles (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S529000, C438S589000

Reexamination Certificate

active

06329253

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an electrostatic discharge device using shallow trench isolation technology in the fabrication of integrated circuits.
(2) Description of the Prior Art
Electrostatic discharge (ESD) refers to a high voltage accidentally applied to an integrated circuit. ESD can result from either automated or human handling. If the voltage applied to the gate insulator becomes excessive, the gate oxide can break down. MOSFET devices are particularly vulnerable to ESD damage. Because of this danger, ESD protection transistors are fabricated to direct ESD current away from the circuit it is protecting.
Shallow trench isolation (STI) is widely used in integrated circuit manufacturing. One conventional STI process is illustrated in
FIGS. 1-3
. Referring to
FIG. 1
, there is shown a trench etched into the semiconductor substrate
10
. The trench is filled with a dielectric layer
12
by any of a variety of gap-filling methods. In order to avoid dishing of the STI region during polishing, such as by chemical mechanical polishing (CMP), a reverse trench mask
15
is formed over the trench. Most of the dielectric layer
12
is etched away where it is not covered by the mask
15
. The mask is removed and the dielectric layer is planarized to the surface of the substrate, as shown in FIG.
3
.
The present invention uses a method similar to this STI technology to form an ESD device.
A number of patents present a variety of methods to form ESD devices. U.S. Pat. No. 5,629,544 to Voldman et al teaches forming an ESD gate partially over an STI region. U.S. Pat. No. 5,744,841 to Gilbert et al shows a halo region around the source and/or drain to optimize breakdown voltage and shows an ESD gate over a field oxide regions. U.S. Pat. No. 5,918,117 to Yun shows a method of forming an ESD device. U.S. Pat. No. 5,885,875 to Hsu discloses an ESD device over a field oxide region and an ESD implant under the field oxide region.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the invention is to provide a process for forming an electrostatic discharge device in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming an electrostatic discharge device using shallow trench isolation technology.
Another object of the invention is to provide a process for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology.
In accordance with the objects of the invention, a method for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology is achieved. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. The oxide within the trench is partially etched away leaving the oxide on the sidewalls and bottom of the trench. The oxide is polished away to the surface of the semiconductor substrate whereby oxide remains only on the sidewalls and bottom of the trench. A gate is formed within the trench whereby the gate is surrounded by the oxide. First ions are implanted into the semiconductor substrate adjacent to the trench to form N-wells. Second ions are implanted into the semiconductor substrate in a top portion of the N-wells to form source/drain regions. Third ions are implanted into the semiconductor substrate underlying the trench. Optionally, ions are implanted underlying the N-wells to form electrostatic discharge trigger taps. This completes formation of an electrostatic discharge device in the fabrication of integrated circuits.


REFERENCES:
patent: 5399515 (1995-03-01), Davis et al.
patent: 5567634 (1996-10-01), He'bert et al.
patent: 5629544 (1997-05-01), Voldman et al.
patent: 5723376 (1998-03-01), Takeuchi et al.
patent: 5744841 (1998-04-01), Gilbert et al.
patent: 5885875 (1999-03-01), Hsu
patent: 5918117 (1999-06-01), Yun
patent: 5963799 (1999-10-01), Wu
patent: 6051488 (2000-04-01), Lee et al.
patent: 6066532 (2000-05-01), Chen et al.
patent: 6197661 (2001-03-01), Mogami et al.

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