Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1998-03-26
2001-11-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S421000, C438S440000, C438S449000
Reexamination Certificate
active
06313006
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application Serial No. 87100223, filed Jan., 9, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of ion implantation, and more particularly to a method of field implantation in a dynamic random access memory (DRAM). The predetermined source/drain region of a subsequently formed transistor is covered and implanted with high concentration ions. An ion field is formed, so that in the transistor, no ion field is formed underneath the source/drain region. In addition to the function of device isolation, the ion field effectively reduces the junction capacitance and leakage current. Moreover, the sensitivity of data access is enhanced.
2. Description of the Related Art
In
FIG. 1
, a conventional method of field implantation is shown. On a substrate
10
, for example, a P-type substrate, a field oxide layer
30
is formed. According to a required depth, P-type ions are implanted to the substrate
10
. A P-type ion field to increase the doping concentration under the channel, or as a device isolation, or a P-field, is formed by the P-type ions
20
a
in the substrate
10
. Similarly, if an N-type substrate is in use, N-type ions are implanted to form an N-type ion field (N-field).
In
FIG. 2
, a DRAM formed by using the substrate is shown in FIG.
1
. The method of forming the DRAM is not described here for it is a well-know technique. The disadvantages of the method are as follows.
1. The junction gradient between the connecting point
210
and the substrate
10
is too high, so that the leakage current is increased.
2. In the area of the bit line connecting point, the very high junction gradient causes a larger junction capacitance between the bit line and the substrate.
3. As the junction capacitance between the bit line and the substrate increases, the ratio of Cb/Cs is increased to lower the sensitivity of data access.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of field implantation. The junction gradient between the substrate and the bit line is decreased, so that the leakage current and the junction capacitance are increased, and the sensitivity of data access is increased.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of field implantation. On a semiconductor substrate, a field oxide layer is formed. A photo-resist layer is formed and patterned on substrate as a mask for the subsequent ion implantation. A first type ion is implanted into a predetermined depth of the substrate. The photo-resist layer is removed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4437225 (1984-03-01), Mizutani
patent: 4786614 (1988-11-01), Cogan
patent: 4912062 (1990-03-01), Verma
patent: 4959325 (1990-09-01), Lee et al.
patent: 5885886 (1999-03-01), Lee
patent: 5895252 (1999-04-01), Lur et al.
patent: 5940715 (1999-08-01), Hayashi
patent: 5986314 (1999-11-01), Seshadri et al.
Chien Sun-Chieh
Hsue C. C.
Jones Josetta I.
Niebling John F.
United Microelectronics Corp.
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