Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1998-06-30
2001-03-13
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C714S700000
Reexamination Certificate
active
06201746
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test method for testing semiconductor memory devices. More particularly, the present invention is directed to method of testing high speed memory devices using a relatively slow tester by defining the timing conditions of tester signals thereby preventing interferences with memory device signals.
2. Description of the Related Arts
In order to improve the operating speed of memory devices, a fast page (FP) mode and an extended data out (EDO) mode, also referred to as hyper page mode, are used in Dynamic Random Access Memory (DRAM) devices.
FIG. 1
is a timing diagram of the conventional DRAM operating in the FP mode. In the FP mode, the DRAM allows faster data operations within a page boundary defined by a valid row address being available at the falling edge of the Row Address Strobe (RAS/) signal. This is accomplished by holding the RAS/ signal low and toggling the Column Address Strobe (CAS/) signal so that a plurality of memory cells connected to the same row are sequentially selected by valid column addresses at subsequent falling edges of the CAS/ signal. Data operations for one page end when both the RAS/ and the CAS/ signals change from an active logic low state to an inactive logic high state.
The Write Enable (WE/) signal is used to select between read and write operations in the DRAM. When the WE/ signal is at a logic high, the DRAM reads out data. The access time from the RAS/ signal t
RAC
is defined as the time between the falling edge of the RAS/ signal and the time when the first data output is valid. The access time from the CAS/ signal t
CAC
is defined as the time between the falling edge of the CAS/ signal and the time when the first data output is valid. The access time from the column address t
AA
is time between the input of a valid column address and the time when the first data output is valid. These time parameters bound the operational speed of the DRAM. The cycle time of the FP mode t
PC
is measured from a first transition of the CAS/ signal from a logic low state to a logic high state to a second transition of the CAS/ signal from a logic low to a logic high state in a single page. The CAS/ signal precharge time t
CP
indicates when the CAS/ signal is in its inactive precharge state. Generally, the shorter the FP mode cycle time t
PC
and the shorter the CAS/ precharge time t
CP
, the faster data is outputted from the DRAM. Therefore, the operational speed of the DRAM can also be defined by t
PC
and t
CP
time parameters.
FIG. 2
is a timing diagram of a conventional DRAM operating in the EDO mode. In the EDO mode, the DRAM operates similarly to the FP mode DRAM but at a faster cycle rate. The faster cycle rate is accomplished by deactivating the CAS/ signal by transitioning the CAS/ signal from a logic low to a logic high state. Deactivating the CAS/ signal results in the CAS/ signal no longer controlling the output buffer. By doing so, a pipelined data flow is provided allowing data to be read and processed faster. In general, the extended output is accomplished by configuring the DRAM, such as a FP mode DRAM, so that the CAS/ signal no longer tristates the I/O buffer when CAS/ goes into the precharge state. In the EDO DRAM, the data precharge time caused by the CAS/ signal does not exist thereby reducing the data fetch time and the operational cycle time of the device.
Accordingly, the EDO DRAM requires the data output hold time t
DOH
, the data access time t
CPA
, the EDO mode cycle time (hyper page cycle time) t
HPC
, and the CAS/ signal precharge time t
CPA
, in addition to the constraints imposed by the time parameters t
RAC
, t
CAC
, and t
AA
. The data output hold time t
DOH
is defined as the data hold time after the CAS/ signal changes from a logic high to a logic low state. The access time t
CPA
is measured from the CAS/ signal precharge to the next data output. The hyper page cycle time t
HPC
is a complete period of the CAS/ signal. Finally, the CAS/ precharge time t
CP
is measured from a logic low to high transition of the CAS/ signal to a logic high to low transition of the CAS/ signal.
A high speed tester is required to functionally test the FP and EDO mode DRAM devices described above. However, high speed testers are expensive resulting in high equipment investment costs. Additionally, the technological advances of the test equipment do not track the rapid progress of the memory devices. Accordingly, it is desirable to test high speed memory devices using existing low speed test equipment thereby reducing the initial equipment investment and the time to market of newly developed DRAM devices.
The M9600 Memory Device Tester from MINATO of Japan is an example of a low speed tester. The M9600 tester has a maximum frequency of 33 MHZ (30 ns clock period) and a usable rate range from 30 ns to 4 ms. Thus, it is impossible to realize an EDO mode cycle time t
HPC
of 20 to 25 ns necessary to test 50 ns/60 ns 16M EDO DRAM. This problem is overcome by using a clock modulation technique disclosed in co-pending patent application Attorney Do. No. 9903-5, filed herewith, titled TEST METHOD OF INTEGRATED CIRCUIT DEVICES BY USING A DUAL EDGE CLOCK TECHNIQUE by the same assignee.
In the meantime, when a slow tester such as the M9600 tester is used to test FP and EDO mode DRAMs, the test cycle timing must be modified to avoid interferences between slower frequency tester signals and higher frequency Device Under Test (DUT) signals.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the disadvantages associated with prior art test methods and circuits therefor.
It is another object of the present invention to overcome the timing limitations of low speed testers.
It is yet another object of the present invention to provide a test method by which high speed memory devices can be tested using relatively low speed testers.
It is yet another object of the present invention to establish timing conditions for a number of signals supplied from the low speed tester to the DUT.
According to the present invention, a shift signal and a strobe signal are generated from a tester. The shift signal controls a driver switch and a comparator switch, and the strobe signal enables a comparator. By supplying the shift signal within a predetermined time range, the usable range of the strobe signal, and thus of the tester, expands and new timing conditions for the clock signals in the test cycle can be obtained.
According to the timing conditions of the tester signals, the shift signal of a read operation in read-and-then-write sequence of operation must be equal to or less than the activation of the WE/ signal of the next cycle when the operational timing is a one-rate cycle condition in which the strobe signal is within the test cycle. In a write-and-then-read sequence of operations, the shift signal must begin at the same time or earlier than the activation of the OE/ signal of the next cycle.
When the operational timing is a two-rate cycle condition in which the strobe signal occurs outside of the test cycle, the maximum shift clock signal has to meet the condition of ‘next test cycle—dead zone’, and the minimum shift clock has to meet the condition of ‘test cycle+shift clock≧strobe signal+dead zone’ in consideration that the test cycle must larger than the strobe signal by over the dead zone in the one-rate cycle condition.
REFERENCES:
patent: 3976940 (1976-08-01), Chau et al.
patent: 4929888 (1990-05-01), Yoshida
patent: 5809034 (1998-09-01), Rezvani et al.
Bang Jeong-Ho
Koo Ja-hyun
Shim Hyun-seop
Tcho Jong-bok
Marger & Johnson & McCollom, P.C.
Phan Trong
Samsung Electronics Co,. Ltd.
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