Simplifying conductive plate/via isolation

Details Simplifying conductive plate/via isolation Simplifying conductive plate/via isolation

1999-06-03

2001-08-07

Mills, Gregory (Department: 1763)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S254000, C438S255000, C438S700000, C438S734000, C438S739000, C134S001200

Reexamination Certificate

active

06271078

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, especially to the fabrication of DRAM Arrays.
Background: Capacitor-Under-Bitline DRAM
DRAM cells have a capacitor buried under, or stacked over, the transistor associated with it. Where the capacitor is stacked over the transistor, there are two types of cells: the Capacitor Over Bitline (COB) cell and the Capacitor Under Bitline (CUB).
FIG. 4
shows an example of a CUB DRAM architecture, with capacitor structures
30
, composed of the conductive storage node layer
16
, dielectric layer
18
, and plate layer
20
, rising above the gates
10
of the transistors in the DRAM array. The use of polysilicon to form the conductive plate layer is changing to the use of metals, such as TiN, to avoid depletion layer formation in the capacitor, which in turns lowers cell capacitance. Bitline
22
runs above the capacitors, with the bitline contact
24
descending through the top capacitor electrode (plate)
20
to contact underlying devices or risers, such as the bitline contact plug
12
. As the bitline contact is etched through the conductive plate layer of the capacitor, shorting to this plate by the via must be avoided at all costs, or the DRAM will lose functionality due to inadvertent capacitor leak-age/discharge. Current state-of-art technology utilizes the following flow:
a.) Etch via through the capacitor plate;
b.) Ash and post-etch clean (in no particular order);
c.) Wet etch to isotropically remove that portion of the plate which is immediately adjacent to the via, with e.g. H2O2- or HF-containing aqueous solutions;
d.) conformal deposition and etchback of dielectric
26
, generally SiN or SiO2, which insulates the via/plate junction (or partial oxidation of the plate layer if it is still polysilicon).
Simplifying Plate/Via Isolation in CUB DRAM
The present application discloses using a dry (plasma) process to accomplish both the post-etch clean and wet etch steps. Previous work has shown that the use of dilute CFx, in O2-rich remote plasmas will isotropically etch TiN from the top of A1 metallizations. Using this process to remove post-etch residue from the via replaces expensive and environmentally-unfriendly solvent cleans, while simultaneously retracting the capacitor plate material from the via sidewalls.
Advantages of the disclosed methods and structures include simplification of the fabrication process, which in turn reduces costs.


REFERENCES:
patent: 04-134856 (1992-05-01), None

Affiliated with

Also associated with

Rating

Simplifying conductive plate/via isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Simplifying conductive plate/via isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simplifying conductive plate/via isolation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2477340