Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
2002-09-27
2004-02-24
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C438S800000, C414S935000, C414S937000, C414S940000
Reexamination Certificate
active
06696367
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication, and more particularly to improved wafer handling systems.
BACKGROUND OF THE INVENTION
Semiconductor wafers or other such substrates typically arrive at the input of a process tool as a group carried in a wafer carrier and from this input must be transported among the internal stations of a process tool. In furtherance of this task, wafer handling systems facilitate the transfer of wafers from one station to another. During this process, it is very important that the wafer be kept isolated from contamination. The presence of contaminant particles on the surface of a wafer can lead to the formation of defects during the fabrication process. Therefore, the wafers must be moved between isolated interior chambers of a process tool in such away as to minimize contamination of both the wafers themselves and the possibility of the cross contamination of chambers.
In furtherance of minimizing wafer contamination, it is desirable to minimize the amount of time a wafer is exposed to contaminants. One way to minimize contaminants is to use standardized front opening unified pods (FOUPs).
Another approach to minimizing wafer exposure to the ambient environment (e.g., clean room) is to use a large capacity loadlock chamber (e.g., 25 wafers) capable of receiving an entire cassette or FOUP of wafers. However, large capacity loadlock chambers pose a number of problems including requiring complex elevator mechanisms, which require an even larger volume. The elevator mechanisms require extra chamber “headroom” in order to have space to raise and lower the load of wafers, allowing access by single wafer robots. Due to the large internal volume of high capacity loadlock chambers, longer purge cycles are necessary to remove potentially wafer damaging agents, such as oxygen and moisture. During these purge cycles, wafer processing is delayed while waiting on the completion of the purging. In systems where two loadlock chambers are employed the footprint of the fabrication tool can also increase substantially. In addition, the use of an elevator mechanism reduces the uptime and system availability, and further increases the risk of particle generation caused by the moving components of the elevator.
Wafer handling systems typically employ robot arms in order to effectively transfer wafers between stations. On the end of each of these arms, an end effector is configured to gain access to a wafer at a first station, lift the wafer, transport the wafer, gain access to the second station, and then deposit the wafer at the second station.
The cost of processing semiconductor wafers, always a prime consideration, is often evaluated by the throughput per unit of cost. Another measure of cost is the throughput per area of floor space, wherein it is desirable to reduce the footprint of the apparatus employed. Related to both is the importance of reducing the capital cost of the equipment. In an industry in which the speed of processing is directly related to output, additional handling steps slow down the fabrication line. Therefore, advancements that can improve the competitive edge by either measure are highly desirable.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a semiconductor processing tool is provided comprising a first substrate handling chamber, a front docking port located on the outside surface of the first substrate chamber, and a robot arm located in the front wafer handling chamber. In addition, a loadlock chamber is joined to the first substrate handling chamber and a buffer station is located between the loadlock chamber and the front docking ports. The buffer station is configured to provide a less contaminated inert internal environment as compared with the internal environment of a cassette docked to the docking port. The buffer station also has a rack configured to have multiple shelves for holding substrates.
In accordance with one aspect of the present invention, a method of fabricating an integrated circuit is also provided comprising first docking a substrate cassette with a front docking port of a process tool. A substrate is then transferred to a buffer station located between the docking port and a loadlock chamber and the buffer station is then purged. The substrate is then moved from the buffer station to the loadlock chamber.
Preferred embodiments of the present invention employ a buffer station having a rack with reduced pitch, or relative spacing between shelves, as compared to standard cassettes or FOUPs for the same size of substrate. Thus, the preferred buffer stations have a low volume that can be quickly and efficiently purged to provide a clean, nonoxidizing environment.
The preferred embodiments offer many advantages. Embodiments employing buffer chambers, which are small and easily purged, serve as quickly accessible and less contaminated chambers to temporarily store wafers during processing. Reduced pitch buffer station racks also enable access to all shelves by a standard robot arm, without the need for a internal elevator mechanism in the buffer stations. Consequently, the absence of the extra movement inherent with an internal elevator decreases the generation of contaminants inside the process tool.
Certain preferred embodiments employ a variable pitch end effector in order to adjust the relative spacing of the end effector wafer supports. This allows the end effector to simultaneously transfer a plurality of wafers between racks, even though the racks have a different relative spacings between support slots shelves.
For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
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SEMI E62-0997 Provisional Specification for 300-mm Front-Opening Interface Mechanical Standard (FIMS).
Aggarwal Ravinder
Alexander Jim
Kusbel Jim
ASM America Inc.
Ghyka Alexander
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