System and method for evaluating a multiprocessor system...

Details System and method for evaluating a multiprocessor system... System and method for evaluating a multiprocessor system...

2007-06-26

2007-06-26

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S742000

Reexamination Certificate

active

10278578

ABSTRACT:
A system and method for evaluating a multiprocessor system having multiple processors coupled via a system bus is disclosed. A test vector is executed on a processor under test. While the test vector is being executed, an instruction that causes a transaction to be issued on the system bus is executed on another processor, thereby stressing the first processor.

REFERENCES:
patent: 4475195 (1984-10-01), Carey
patent: 4622669 (1986-11-01), Pri-Tal
patent: 4961140 (1990-10-01), Pechanek et al.
patent: 5548713 (1996-08-01), Petry et al.
patent: 5646949 (1997-07-01), Bruce, Jr. et al.
patent: 5724527 (1998-03-01), Karnik et al.
patent: 5787270 (1998-07-01), Bloomer et al.
patent: 5954824 (1999-09-01), Cherichetti et al.
patent: 6018808 (2000-01-01), Schieve
patent: 6058253 (2000-05-01), Lowe
patent: 6253344 (2001-06-01), Fin et al.
patent: 6877053 (2005-04-01), Lahiri et al.
IBM, “SPD Bus Throughput Accelerator”, IBM Technical Disclosure Bulletin, Sep. 1, 1987, vol. 30, pp. 1828-1829.

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