Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-04
2011-01-04
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07865849
ABSTRACT:
A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.
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Butler Kenneth M.
Carulli, Jr. John M.
Saxena Jayashree
Vasavada Amit P.
Brady III Wade J.
Dimyan Magid Y
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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