Structure for bumped wafer test

Details Structure for bumped wafer test Structure for bumped wafer test

2011-03-08

2011-03-08

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S612000, C438S614000, C257SE23021, C324S754090

Reexamination Certificate

active

07901956

ABSTRACT:
A semiconductor package includes a substrate having a bond pad disposed on a top surface of the substrate. A first passivation layer is formed over the substrate and bond pad. The first passivation layer has an opening to expose the bond pad. An under bump metallurgy is formed over the first passivation layer. An end of the under bump metallurgy extends beyond an end of the bond pad. A second passivation layer is formed over the under bump metallurgy. The second passivation layer has a first opening to expose a first surface of the under bump metallurgy, and a second opening which is etched to expose a second surface of the under bump metallurgy. A solder ball is attached to the first surface of the under bump metallurgy to provide electrical connectivity. The second opening in the second passivation layer receives a probe needle to test the semiconductor device.

REFERENCES:
patent: 6878963 (2005-04-01), Fang
patent: 2004/0089954 (2004-05-01), Hembree et al.

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