Storage poly process without carbon contamination

Details Storage poly process without carbon contamination Storage poly process without carbon contamination

1999-07-27

2002-04-16

Gulakowski, Randy (Department: 1746)

Etching a substrate: processes

Gas phase etching of substrate

Application of energy to the gaseous etchant or to the...

C216S064000, C216S079000, C438S710000, C438S719000

Reexamination Certificate

active

06372151

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a process and apparatus for etching silicon. More specifically, the present invention relates to etching polysilicon to form structures, such as storage nodes, that are used in the fabrication of integrated circuits.
Dynamic Random Access Memory (DRAM) devices include arrays of memory cells. Each memory cell includes a single access transistor and a storage capacitor. As device sizes shrink and more and more transistors are squeezed into a fixed area of an integrated circuit, DRAM capacity has increased. It has been suggested, however, that the capacitance of the storage capacitor must have a minimum level in order to send a sufficiently strong signal to the sense circuitry and provide sufficient immunity to soft errors. For example, it has been suggested that the storage capacitor of a one Gigabit DRAM should have a capacitance of between 25-40 femto Farads (fF) in order to provide reliable operation. This minimum capacitance believed to be required for DRAM devices has not been reduced in proportion to the size reduction of the access transistors. Thus, the size of the storage capacitor is an important factor in the overall capacity of a DRAM device. In order to continue to increase the density of DRAM devices, semiconductor manufacturers have been required to develop methods to increase the storage capacity of a memory cell capacitor per unit area.
There are two main approaches to increasing the storage capacity of such capacitors. The first is to increase the dielectric constant of the insulating material. The second is to increase the storage area of the capacitor electrodes. A combination of both approaches has been used over the years as DRAM capacity has increased from the thousand-bit level (K-bit) to the million-bit level (M-bit) and now to the billion-bit level (G-bit).
One approach that has been used to increase the storage area of the capacitor electrodes has been to form what are known as stacked capacitors or stacked planar capacitors, as opposed to planar capacitors that were used in early DRAM devices. Stacked capacitors involve building a primarily vertical, as opposed to horizontal capacitor structure, in order to reduce the amount of chip real estate required by the capacitor. Stacked planar capacitors are, as their name implies, capacitors that achieve their capacitance requirements using both vertical and horizontal structures.
There are a number of different types of stacked or stacked planar capacitors that involve various three dimensional shapes. Some of these different capacitors, as referred to by those of skill in the industry, include box capacitors, fin-shaped capacitors, hammer capacitors, crown capacitors and cylindrical capacitors among others. At least some of these structures can be formed by depositing a relatively thick polysilicon layer and etching the layer to form vertical protrusions. These protrusions have been on the order of 5-6,000 Å deep in currently available DRAM devices such as 64 M-bit devices, and can be on the order of 8-10,000 Å or deeper in the next generation of DRAM devices.
FIG. 1
shows an example of such polysilicon protrusions. In
FIG. 1
a polysilicon layer
15
is deposited over a silicon substrate
10
. Polysilicon layer
15
has been etched using a photoresist mask
20
to define protrusions
15
a
,
15
b
. In the exemplary device shown in
FIG. 1
, protrusions
15
a
,
15
b
have a height of approximately 10,000 Å and are separated by approximately 0.3 &mgr;m. A trench
25
is formed between protrusions
15
a
,
15
b
. Trench
25
has a depth equal to the height of the protrusions and a width equal to the distance between the protrusions. The ratio of the trench depth to the trench width is referred to as the aspect ratio of the trench.
One known process that has been used to etch polysilicon to form protrusions such as
15
a
,
15
b
shown in
FIG. 1
forms a plasma from sulfur hexafluoride (SF
6
), hydrogen bromide (HBr) and molecular oxygen (O
2
). This etch process has been sufficient to form the protrusions included in some stacked capacitors but the process has limited commercial applicability to future devices because of its etch selectivity (generally less than 2:1) and etch rate (generally less than 4-5,000 Å/min).
Another method to form protrusions
15
a
,
15
b
forms a plasma from SF
6
, a fluorocarbon, such as CHF
3
, and O
2
. This process can provide sufficient etch selectivity (greater than 3:1) and a sufficient deposition rate (greater than 10,000 Å/min) to meet the requirements of many different DRAM manufacturers. Some manufacturers, however, desire alternative methods to form protrusions
15
a
,
15
b
to meet other criteria. For example, one prominent DRAM manufacturer requires that the polysilicon etchant chemistry provide an etch selectivity to photoresist of at least 3:1, an etch rate of at least 10,000 Å/min and not include carbon in the etchant gas.
SUMMARY OF THE INVENTION
The present invention provides a new method for etching silicon, and in particular polysilicon, that provides improved etch rate and photoresist etch selectivity as compared to an SF
6
/HBr/O
2
etch process and does not include a fluorocarbon etchant gas or any other carbon-containing gas. The method of the present invention provides polysilicon etch rates of close to or greater than 15,000 Å/min and a photoresist-to-polysilicon etch selectivity of 3:1 and higher. The method of the present invention also provides for either vertical or slightly tapered etch profiles. These and other characteristics of the method of the present invention make it ideal for forming storage nodes and other structures that are used in the fabrication of 1 GB DRAMs and in the fabrication of projected future DRAMs.
The method of present invention etches a layer of polysilicon formed on a substrate disposed within a substrate processing chamber. The method flows an etchant gas including sulfur hexafluoride, oxygen and nitrogen into the processing chamber and ignites a plasma from the etchant gas to etch the polysilicon formed over the substrate.
In one embodiment the etchant gas includes sulfur hexafluoride (SF
6
), molecular oxygen (O
2
) and molecular nitrogen (N
2
). The volume ratio of molecular oxygen to the sulfur hexafluoride is between 0.5:1 and 1:1 inclusive and the volume ratio of the sulfur hexafluoride to molecular nitrogen is between 1:1 and 4:1 inclusive. In a preferred embodiment, the etchant gas consists essentially of SF
6
, O
2
and N
2
. In an even more preferred embodiment, the volume ratio of O
2
to sulfur hexafluoride is between 0.8:1 and 1:1 inclusive and the volume ratio of sulfur hexafluoride to N
2
is between 1.5:1 and 2:1 inclusive.
In another embodiment the etchant gas includes sulfur hexafluoride, nitrous oxide (N
2
O) and molecular oxygen. The volume ratio of SF
6
to nitrous oxide is between 1:1 and 4:1 inclusive and the volume ratio of O
2
to SF
6
is between 0.25:1 and 0.5:1 inclusive. In an even more preferred version of this embodiment, the volume ratio of SF
6
to N
2
O is between 1.5:1 and 2:1 inclusive and the ratio of O
2
to SF
6
is between 0.4:1 and 0.5:1 inclusive.
These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached figures.


REFERENCES:
patent: 4330384 (1982-05-01), Okudaira et al.
patent: 4352724 (1982-10-01), Sugishima et al.
patent: 4431477 (1984-02-01), Zajac
patent: 4502915 (1985-03-01), Carter et al.
patent: 4595484 (1986-06-01), Giammarco et al.
patent: 4615764 (1986-10-01), Bobbio et al.
patent: 5047115 (1991-09-01), Charlet et al.
patent: 5095346 (1992-03-01), Bae et al.
patent: 5180464 (1993-01-01), Tatsumi et al.
patent: 5399518 (1995-03-01), Sim et al.
patent: 5401356 (1995-03-01), Enami et al.
patent: 5569356 (1996-10-01), Lenz et al.
patent: 5693182 (1997-12-01), Mathuni
patent: 5712813 (1998-01-01), Zhang
patent: 5721090 (1998-02-01), Okamoto et al.
patent: 5

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