SOI wafer and process for producing it

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S347000, C257SE27112, C257SE21320

Reexamination Certificate

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07122865

ABSTRACT:
An SOI wafer, includes a substrate made from silicon, an electrically insulating layer with a thermal conductivity of at least 1.6 W/(Km) and a single-crystal silicon layer with a thickness of from 10 nm to 10 μm, a standard deviation of at most 5% from the mean layer thickness and a density of at most 0.5 HF defects/cm2.A process is for producing an SOI wafer of this type, in which a substrate wafer made from silicon is joined to a donor wafer via a layer of the electrically insulating material which has previously been applied. The donor wafer bears a donor layer of single-crystal silicon, with a concentration of vacancies of at most 1012/cm3and of vacancy agglomerates of at most 105/cm3. After the wafers have been joined, the thickness of the donor wafer is reduced in such a manner that the single-crystal silicon layer having these properties is formed from the donor layer, this single-crystal silicon layer being joined to the substrate wafer via the layer of electrically insulating material.

REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 5413952 (1995-05-01), Pages et al.
patent: 5930643 (1999-07-01), Sadana et al.
patent: 6232142 (2001-05-01), Yasukawa
patent: 6326279 (2001-12-01), Kakizaki et al.
patent: 6403450 (2002-06-01), Maleville et al.
patent: 6566255 (2003-05-01), Ito
patent: 6608327 (2003-08-01), Davis et al.
patent: 2002/0094663 (2002-07-01), Holman
patent: 2002/0167068 (2002-11-01), Hsu et al.
patent: 2003/0203657 (2003-10-01), Ito
patent: 2004/0108537 (2004-06-01), Tiwari
patent: 2004/0115905 (2004-06-01), Barge et al.
patent: 2005/0133866 (2005-06-01), Chau et al.
patent: 2005/0287767 (2005-12-01), Dantz et al.
patent: 1132408 (1996-10-01), None
patent: 4414947 (1995-08-01), None
patent: 69225911 (1998-06-01), None
patent: 10131249 (2002-05-01), None
patent: 533551 (1993-03-01), None
patent: 707 338 (1996-04-01), None
patent: 829559 (1998-03-01), None
patent: 674806 (1998-06-01), None
patent: 866150 (1998-09-01), None
patent: 905767 (1999-03-01), None
patent: 1 225 625 (2002-07-01), None
patent: 03/003430 (2003-01-01), None
Patent Abstract of Japan corresponding to JP 01-315129.
Patent Abstract of Japan corresponding to JP 03-069144.
Patent Abstract of Japan corresponding to JP 03-069145.
Patent Abstract of Japan corresponding to JP 09-162088.
English Derwent Abstract AN 1998-161363 corresponding to EP0829559.
English Derwent Abstract An 1995-303208 corresponding to DE 44 14 947.
English Derwent Abstract AN 1998-482980 corresponding to EP 0 866 150.
Handbook of deposition technologies for films and coatings, R.F. Bunshah, 1994, 2nd ed., p. 184ff, p. 134ff.
English Derwent Abstract AN 1993-095807 corresponding to EP0533551.
Enlish Derwent Abstract AN 2002-464528 corresponding to DE 101 31 249.
English Derwent Abstract AN 1998-009490 corresponding to CN 1132408 A.

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