SOI semiconductor integrated circuit for eliminating...

Details SOI semiconductor integrated circuit for eliminating... SOI semiconductor integrated circuit for eliminating...

2002-12-27

2004-03-09

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S300000

Reexamination Certificate

active

06703280

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to silicon-on-insulator (SOI) technology, and more particularly to an SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and a method of fabricating the same.
DESCRIPTION OF THE RELATED ART
In the semiconductor manufacturing industry, there has been a great deal of attention paid to reducing parasitic capacitance and resistance to increase the operating speed of semiconductor integrated circuits. SOI MOSFETs have been demonstrated to be superior to bulk silicon MOSFETs in terms of low power, high speed very large scale integration (VLSI) applications because of their inherent merits such as less junction capacitance and better device isolation. In addition, there are many advantages in SOI devices such as better immunity to soft errors, reduction in dynamic power, improvement in latch-up resistance even with increased packing density. Despite the above outstanding features of SOI devices, Sol integrated circuits have suffered some lack of commercial success due to technical problems in material processing and device design.
FIG. 1
depicts a typical structure of an SOI MOSFET according to the prior art. The SOI MOSFET includes a gate electrode
20
, a gate dielectric
21
, a source
23
and drain
24
on insulating layer
15
. A backside surface of the insulating layer
15
is in contact with a supporting substrate
10
.
Since the body region
30
of the SOI MOSFET is isolated by the insulating layer
15
, it is electrically isolated and therefore its voltage varies with the voltage applied to either source region
23
, drain region
24
, or gate electrode
20
.
The voltage fluctuation of the body region
30
in SOI MOSFET, commonly referred to as the floating body effect (FBE), causes detrimental effects for the proper operation of SOI devices. The most common of these detrimental effects are the kink effect and the bipolar effect. With the channel region of the device partially depleted and a high drain voltage applied, the electric field created in the device causes impact ionization near the drain region
24
.
Accordingly, in the event that the SOI MOSFET is an SOI N-MOSFET, the generated holes are injected into the body thereby creating a positively charged body. The first consequence of this positive charge accumulated in the body
30
is the increase of the body potential resulting in a decrease of the threshold voltage (V
T
) of the SOI MOSFET. Since the decrease of the threshold voltage raises the drain current, the variation of threshold voltage shows up as kinks in the output characteristics of the SOI MOSFETs.
Another consequence of the voltage increase is the eventual turn-on of the lateral bipolar structure since the MOSFET includes a lateral bipolar transistor, i.e., the n-p-n construction
23
,
30
, and
24
. As the body
30
of the MOSFET becomes positively biased, the source-body (
23
-
30
) junction, corresponding to emitter-base junction of the lateral n-p-n construction, becomes forward biased, and electrons are injected from the source
23
into the body region
30
. The injected electrons reaching the drain depletion region add to the drain current. Consequently, the drain current is dominantly controlled by the parasitic bipolar transistor rather than by the channel current under the gate electrode control. This effect is referred to as the parasitic “bipolar” effect. The parasitic bipolar action of the SOI MOSFET induces a “dynamic leakage current”(DLC) especially in a switching circuit.
In a MUX (multiplexer) circuit as depicted in
FIG. 2A
, if the applied voltages at nodes A and B are high, then the output node C will be high. If the gate voltage of the node A is switched to a low voltage, then the output node C should be kept to a high voltage. However, in a state that the nodes A and C keep a low voltage and a high voltage, respectively, if the voltage at node B is switched to a low voltage for some reason, the output voltage at node C drops instantaneously by the dynamic leakage mechanism due to the parasitic bipolar effect.
FIG. 2B
illustrates the instantaneous drop of the output voltage at node C in the multiplexer circuit according to the prior art. Here, the x-axis represents time (t) and the y-axis represents voltage of the node C.
In order to remedy those detrimental effects due to the floating body effect observed in SOI MOSFETs, several technical approaches have been proposed. For instance, F. Assaderaghi et al. proposed a technique for reducing the floating body effect in their technical paper entitled, “A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation,” published in IEEE Electron Device Lett., pp.510-512, Vol.15, No. 12, 1994. F. Assaderaghi et al. tried to eliminate the floating body effect by tying the floating body to the gate of the SOI MOSFET. However, since the dynamic leakage current cannot be avoided between source and drain when the gate voltage is high while keeping source and drain low, they pointed out that their approach is only applicable to the low voltage operation.
As another approach to resolve the floating body problem in SOI devices, J. W. Sleight et al. proposed a Schottky body contact technology in a technical paper entitled, “DC and transient characterization of a compact Schottky body contact technology for SOI transistors,” published in IEEE Transactions on Electron Devices, pp. 1451-1456, Vol. 46, No. 7, July 1999. This technical paper provides a self-aligned Schottky diode method for body contacting partially depleted SOI transistors. In their paper, Schottky diodes are placed at source/drain terminals, allowing the floating body to be tied to the source/drain region.
FIGS.3A and 3B
are schematic layout diagrams for implementing body contact tied to source/drain and gate, respectively, according to the prior art. Referring to
FIG. 3A
, n
+
source
23
is tied to the body
30
through p
+
regions
31
. Referring to
FIG. 3B
illustrating the gate-body contact in accordance with the first prior art paper mentioned above, the body
30
is electrically connected to the gate electrode
20
through electrical contact
33
.
However, it should be noted that the body contacting schemes either to source or gate disclosed in the prior art have fundamental limitations in their application to commercial SOI integrated circuits. Namely, since only the weak parts vulnerable to the dynamic leakage current out of the whole circuit are manually cured by contacting the floating body according to the prior art, it is difficult to resolve the inherent floating body problem in SOI integrated circuits.
For instance, only 50 to 100 thousand transistors are usually body-contacted to remedy the floating body effect out of 1.5 million transistors comprising the 64-bit microprocessor fabricated on SOI substrate.
SUMMARY OF THE INVENTION
In view of these problems, there is need for a method and structure for fundamentally eliminating the floating body effect in SOI semiconductor integrated circuits; which is not subject to these limitations.
Accordingly, it is an object of the present invention to provide a technique to eliminate the floating body effect in SOI integrated circuits. It is another object of the present invention to provide a technique to resolve the kink effect in SOI integrated circuits.
It is another object of the present invention to provide a technique to eliminate the parasitic bipolar effect and consequently the dynamic leakage current in SOI integrated circuits.
It is another object of the present invention to provide a technique to eliminate the floating body effect, which is applicable to commercial SOI products.
It is another object of the present invention to provide a complete solution to eliminate the floating body effect while keeping the conventional layout compatibility.
Accordingly, the invention is directed to a SOI semiconductor integrated circuit and a method of making the same. The SOI integrated circuit of the invention is formed on an SOI substrate including a

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