Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1998-12-23
2003-10-21
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S636000, C438S689000, C438S702000, C438S780000, C257S635000, C257S640000, C257S752000, C257S775000
Reexamination Certificate
active
06635583
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the fabrication of integrated circuits on substrates. More particularly, the invention relates to a low temperature method for producing a low dielectric constant (low &kgr;) silicon carbide film utilizing organosilanes under certain process regimes, which is useful as a low &kgr; anti-reflective coating.
BACKGROUND OF THE INVENTION
Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is the multilevel interconnect technology, which provides the conductive paths between the devices of an integrated circuit (IC) device. The shrinking dimensions of features, presently in the sub-quarter micron and smaller range, such as horizontal interconnects (typically referred to as lines) and vertical interconnects (typically referred to as contacts or vias; contacts extend to a device on the underlying substrate, while vias extend to an underlying metal layer, such as M
1
M
2
, etc.) in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology, has increased the importance of reducing capacitive coupling between interconnect lines in particular. In order to further improve the speed of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and low &kgr; (dielectric constant less than 7.0) insulators to reduce the capacitive coupling between adjacent metal lines. The need for low &kgr; materials extends to barrier layers, etch stops, and anti-reflective coatings used in photolithography. However, typical barrier layer, etch stop, and anti-reflective coating materials have dielectric constants that are significantly greater than 7.0 that result in a combined insulator that does not significantly reduce the dielectric constant. Thus, better materials are needed for barrier layers, etch stops, and anti-reflective coatings in the low &kgr; substrates.
With the change in circuit density, additional process changes are needed. For instance, efforts are being made to improve the photolithography processes for more precise pattern etching. Photolithography is a technique used in making integrated circuits that uses light patterns and typically organic polymers (photoresist materials) to develop fine-scaled patterns on a substrate surface. Photoresist materials typically include, for example, naphthoquinone diazides. In many instances, to properly process the substrate with photolithography and avoid unwanted patterning, the high reflectivity of the layer to be patterned must be ameliorated so light ray reflection is reduced. Reflectivity is usually expressed as a percentage of a known standard, such as bare silicon, having a value of 100%. Extraneous reflections from underlying layers can be reflected to the photoresist and expose the photoresist in undesired areas. Any unwanted exposure can distort the lines, vias, and other features intended to be formed. The reflectivity of damascene structures, discussed below, has increased the need for better photolithography processes.
With multi-layer structures and the increased use of dielectrics, increased reflectivity has contributed to imprecise etching. Dielectric layers are naturally translucent to the ultraviolet light used to expose the photoresist. Thus, multi-level use of dielectrics in the damascene structures results in increased and unwanted reflections. As a result, an anti-reflective coating (ARC) is deposited over the layer to be etched, where the ARC is a thin sacrificial layer that has a lower reflectivity than the underlying layer and is etched by the same or similar chemistries that are used to etch the underlying layer. The ARC reduces or eliminates the extraneous reflections so that improved feature dimensions and accuracy can be more closely spaced, leading to the increased current density desired for ULSI circuits.
ARC materials can be organic or inorganic, as described in U.S. Pat. No. 5,710,067, which is incorporated by reference herein. Organic ARCs include spin-on polyimides and polysulfones, among other materials, and are generally more expensive and require more complex processing than inorganic ARCs. Inorganic ARCs include silicon nitride, silicon oxynitride, &agr;-carbon, titanium nitride, silicon carbide, and amorphous silicon. Prior to the present invention, inorganic ARCs typically were characterized by a high &kgr; value and were not compatible with low &kgr; structures. Use of a high &kgr; ARC partially negates the advantage of changing to low &kgr; materials in that it adds a high &kgr; material to a stack of otherwise low &kgr; layers. In some applications, the high &kgr; ARC can be removed from the substrate, but the removal adds complexity to the processing. Organic ARCs can be used, but they are generally more expensive and require additional processing.
FIG. 1
shows a representation of a substrate with a positive photoresist deposited over a dielectric, as part of the photolithography processing. A positive photoresist develops in the areas exposed to light, whereas a negative photoresist develops in the areas not exposed to light. The integrated circuit
10
includes an underlying substrate
12
having a feature
11
, such as a contact, via, line, or trench. In this patent, “substrate” is used to indicate an underlying material, and can be used to represent a series of underlying layers below the layer in question, such as a barrier layer. A barrier layer
13
may be deposited over the substrate, followed by a dielectric layer
14
. The dielectric layer may be un-doped silicon dioxide also known as un-doped silicon glass (USG), fluorine-doped silicon glass (FSG), or some other low &kgr; material. In this example, an ARC
15
is deposited over the dielectric, followed by a photoresist layer
19
.
The purpose of the ARC is to reduce or eliminate any reflected light waves, typically, by adjusting three aspects of the ARC material—a refraction index (n), an absorption index (k, distinguished from the “&kgr;” of a “low &kgr;” dielectric), and the thickness (t) of the ARC to create a phase cancellation and absorption of reflected light. Typically, the required n, k, and t values depend on the thickness and properties of the underlying layer and need adjustment for each particular application. A computer simulation program, such as one entitled “The Positive/Negative Resist Optical Lithography Model”, v. 4.05, simulates the effect on the n, k, and t values and the reflectivity of the particular layers. The results are analyzed and are typically followed by actual testing and reviewing the results through scanning electron microscopy (SEM) techniques. A proper combination at the various values of n, k, and t is chosen to reduce the reflected light for that application. Because the values of n, k, and t are dependent on each application and each substrate thickness, the proper selection may be time consuming and onerous. In addition, the selection may be only applicable to narrow thickness ranges of the underlying layers which may cause additional difficulties in the repeatability of the deposition process from substrate to substrate.
FIG. 2
is a schematic of the photolithography process in which a light source
23
emits light, such as ultraviolet light, through a patterned template (mask)
21
that defines the pattern of light that will be projected onto the photoresist layer
19
, ultimately resulting in a patterned substrate. The light causes the photoresist in the exposed area
25
to typically change its solubility to organic solvents, for instance, when exposed to violet light. Thus, the exposed areas can be removed by soaking or otherwise cleaning the exposed areas while retaining the unexposed areas.
FIG. 3
is a schematic of the substrate with the feature
27
formed thereon using the etching process. The remainder of the photoresist has been removed, the feature has been etched to the appropriate level, and the substrate is prepared for a
Bencher Christopher
Feng Joe
Huang Judy
Ngai Chris
Shek Mei-Yee
Applied Materials Inc.
Moser Patterson & Sheridan
Rocchegiani Renzo N.
Smith Matthew
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