Shrink test mode to identify Nth order speed paths

Details Shrink test mode to identify Nth order speed paths Shrink test mode to identify Nth order speed paths

2007-07-30

2009-10-20

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

07607061

ABSTRACT:
In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock generator. The first clock generator is coupled to receive an input clock to the integrated circuit and is configured to generate the first clock. The control unit is also coupled to receive a trigger input to the integrated circuit. During a test of the integrated circuit, the control unit is configured to cause the first clock generator to generate the first clock at a first clock frequency, The control unit is configured to cause the first clock generator to generate the first clock at a second frequency greater than the first clock frequency for at least one clock cycle responsive to an assertion of the trigger input.

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patent: 6996021 (2006-02-01), Derner et al.
patent: 6996032 (2006-02-01), Ganry
patent: 7290188 (2007-10-01), Peterson et al.

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