Shallow trench isolation methods employing gap filling doped...

Details Shallow trench isolation methods employing gap filling doped... Shallow trench isolation methods employing gap filling doped...

2000-01-11

2001-04-10

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S430000, C438S433000, C438S434000, C438S435000, C257S520000, C257S521000

Reexamination Certificate

active

06214698

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods for forming trench fill layers in shallow trench isolation (STI) trenches within substrates employed in integrated circuit (IC) fabrication. More particularly, the present invention relates to methods for forming gap filling sub-atmospheric pressure chemical vapor deposition (SA-CVD) doped silicon oxide trench fill layers within shallow trench isolation trenches within substrates employed in integrated circuit fabrication to eliminate voids that may be formed in narrow trenches or those with nearly vertical side walls when filling with dielectric material.
BACKGROUND OF THE INVENTION
Integrated circuits are formed from semiconductor substrates, usually silicon (Si), within and upon whose surfaces are formed active semiconductor regions containing electrical circuit elements that are internally and externally connected to the substrate through multiple patterned conductor layers that are separated by dielectric layers. These active semiconductor regions must be otherwise electrically isolated from adjacent active semiconductor regions by the formation of intervening trenches which are subsequently filled with dielectric material to ensure such electrical isolation and avoid undesired interference between adjacent active semiconductor regions. The continued miniaturization of integrated circuit devices has resulted in smaller trenches formed by, for example, shallow trench isolation (STI) methods to form trench isolation regions essentially co-planar with adjacent active semiconductor regions of the semiconductor substrates.
As noted in U.S. Pat. No. 5,741,740 to Jang et al., it has been found that filling these isolation trenches with gap filling silicon oxide layers through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition methods produce superior results as the silicon oxide layers typically possess the inherently superior gap filling characteristics desirable for trenches of limited dimensions usually present in advanced integrated circuit fabrication.
However, for these increasingly miniaturized integrated circuits with corresponding miniaturized shallow isolation trenches having a width of less than about 0.26 microns, or side walls that are greater than about 80° vertical, an undesired void, or keyhole, is formed within the gap filling silicon oxide layer within the trench. It is easy to form an overhead at the top corners of shallow trenches using traditional CVD-ox (chemical vapor deposition of silicon oxide) to gap filling and thus voids are formed. Void defects may trap contamination or make the final oxide surface of the STI (shallow trench isolation region) lower than the active surface. Also, junction leakage would increase.
For example, U.S. Pat. No. 4,506,435 to Pliskin et al. describes first lining the trench with a silicon oxide lining then filling the trench with, for example, a borosilicate glass. The borosilicate glass layer is heated, causing it to soften and flow to approach planarity. Then the borosilicate glass layer and SiN mask layer are etched to make the borosilicate glass filled trench substantially planar with the SiO masking layer.
U.S. Pat. No. 5,099,304 to Takemura describes a STI fill process that: lines the trench with a silicon oxide lining; forming a silicon nitride (SiN) film over the silicon oxide lining; building a polycrystal silicon film over the SiN film; etching back the polycrystal silicon film below the surface of the semiconductor substrate; then filling the trench with a boron phosphorus doped CVD silicon glass (boron phosphosilicate). The boron phosphorus doped silicon oxide is heated to allow the boron phosphorus doped silicon glass (BPSG) to reflow and make the surface thereof flat. A silicon oxide film, e.g. a boron phosphosilicate glass film is built up by a low pressure CVD method over the semiconductor substrate to make an even flatter surface.
U.S. Pat. No. 4,740,480 to Ooka describes a BPSG isolation fill layer that is fused to flow and reflow to make a smoothly contoured or round surface.
U.S. Pat. No. 5,225,358 to Pasch describes a method where a BPSG layer forms both the STI oxide, filling the trench(es), and the inter level dielectric (ILD) layer after the transistor fabrication process. The BPSG layer is planarized by chemical mechanical polishing (CMP).
U.S. Pat. No. 5,811,345 to Yu et al. describes a SA-CVD-OX trench fill process with an ozone-TEOS layer over a phosphorus doped silicon oxide layer. The ozone-TEOS layer is lowered by a wet dip in HF solution then planarized by plasma etching down to the phosphorus doped silicon oxide layer without CMP being used.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to use doped silicon glass to reflow into voids or keyholes in shallow trench oxides.
Another object of the present invention to use boron-doped silicon glass to reflow into voids or keyholes in shallow trench oxides.
A further object of the present invention is to use three layers to fill a trench, the first layer being a thermal silicon glass liner, the second layer being an undoped SA-CVD (sub-atmosphere chemical vapor deposition) silicon oxide layer, and the third layer being a boron-doped SA-CVD silicon glass layer.
Yet another object of the present invention is to use three layers to fill a trench, the first layer being a thermal silicon glass liner, the second layer being an in-situ deposited undoped SA-CVD silicon oxide layer, and the third layer being an in-situ boron doped SA-CVD silicon glass layer
An additional object of the present invention is to use low content boron (B)-doped SA-CVD oxide to reflow into voids or keyholes in shallow trench oxides to get better gap filling capability than undoped SA-CVD oxide or phosphorus (P)-doped SA-CVD oxide and in that low content B could prevent the B from penetrating to the trench sidewall.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, in a substrate, for example a semiconductor silicon substrate, having a trench with a bottom surface and side walls, undoped silicon glass (USG) liner is grown in the trench to coat the bottom and side walls of the trench with a layer of the USG preferably by a thermal process with the following parameters: from about 800 to 1100° C. This USG liner has a thickness of from about 150 to about 350 Å, and is more preferably 250 Å thick. An undoped silicon oxide layer is then deposited over the undoped silicon glass liner preferably by an SA-CVD process with the following parameters: at about: 60 Torr; a spacing of about 300 mils; about 480° C.; about 5500 sccm O
3
; about 480 mgm (milligrams per minute) TEOS; and at about 4000 sccm He. The undoped silicon oxide layer has a thickness of from about 300 to about 500 Å, and is more preferably 400 Å thick.
A low boron doped silicon oxide is then deposited, preferably by an SA-CVD method, over the undoped silicon oxide layer, filling the trench and covering the surface of the semiconductor integrated circuit. The boron doped silicon oxide layer has a thickness of from about 2500 to about 4500 Å, and is more preferably 3500 Å thick. The boron concentration is from about 2 wt. % to 5 wt. % and more preferably from about 2 wt. % to 3 wt. %. In trenches formed by STI methods having a width of less than about 0.26 microns and/or side walls greater than about 83° vertical, an undesired void or keyhole may be formed within the boron doped silicon oxide layer within the trench. The boron doped silicon oxide layer (B-OX) is then heated to reflow the boron doped silicon oxide into the void, filling and eliminating the void. The B-OX layer is then planarized, preferably by chemical mechanical polishing, CMP, to render the B-OX layer co-planar with the active semiconductor regions within the substrate.


REFERENCES:
patent: 4506435 (1985-03-01), Pliskin et al.
patent: 4740480 (1988-04-01), Ooka
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