Semiconductor integrated circuit device having scan...

Details Semiconductor integrated circuit device having scan... Semiconductor integrated circuit device having scan...

2008-01-15

2008-01-15

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S724000, C714S731000, C714S744000, C365S233100, C327S202000

Reexamination Certificate

active

07320098

ABSTRACT:
A semiconductor integrated circuit device has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.

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UC Berkeley, “Lab 1 Transistors”, Fall 2002, UC Berkeley, pp. 1-5, found on the internet at http://inst.eecs.berkeley.edu/˜cs150/fa02/handouts/2/Lab/lab1.pdf.

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