Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-10-29
2004-06-15
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S745000
Reexamination Certificate
active
06751763
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 200074917, filed on Dec. 9, 2000, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device testing method that is capable of optimizing test time and enhancing test efficiency.
2. Description of Related Art
As the storage capacity of semiconductor memory devices continues to increase, development of a “system-on-chip” has begun, in which a logic circuit and a memory are combined together on one chip. In order to test the functions of a new semiconductor device having a large storage capacity or a complex structure, high-priced testing equipment or new testing programs are typically needed. New equipment or testing programs are expensive, however, and increase the cost of manufacturing semiconductor devices. One way to reduce testing expenses is to reduce the time required to develop new testing programs. Another way is to reduce the time taken to perform the testing program.
A conventional test method for a semiconductor device has fixed test items and a fixed test order, regardless of whether a semiconductor device being tested has a high defect rate or not. Thus, the conventional testing procedure will always perform all of the test items and it will therefore take a certain predetermined amount of time to complete the test. Moreover, as additional kinds of semiconductor devices are developed and as their integration density increases, the number of test items that must be performed to test the functions of these devices also increases. The required testing time is therefore expected to continue to increase.
SUMMARY OF THE INVENTION
To solve these problems, an object of the present invention is to provide a semiconductor device testing method that is capable of reducing testing costs by minimizing testing time.
According to one aspect of the present invention, a method of testing a semiconductor device includes performing a normal test and determining whether predetermined fuzzy conditions are satisfied. If the predetermined fuzzy conditions are satisfied, a fuzzy test is performed. The normal test continues to be performed, however, if the predetermined fuzzy conditions are not satisfied. The method also preferably determines whether a group of tests performed on a predetermined unit have been completed. If that group of tests has not been completed, the method returns to determining whether the predetermined fuzzy conditions are satisfied. The normal test includes a predetermined number of normal test items, while the fuzzy test preferably includes a dynamically adaptable number of fuzzy test items.
According to another aspect of the present invention, a method of testing a semiconductor device includes reading predetermined test information and using the predetermined test information to perform a normal test or a fuzzy test depending on predetermined fuzzy conditions. The order of test items in the normal test can be changed, preferably in relation to an order of defect rates. This test method can further determine which test items should be included in the fuzzy test by selecting desired test items from among the normal test items for inclusion in the fuzzy test.
REFERENCES:
patent: 5600757 (1997-02-01), Yamamoto et al.
patent: 6347386 (2002-02-01), Beffa
patent: 6526008 (2003-02-01), Caponetto et al.
patent: 6622270 (2003-09-01), Beffa
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Ton David
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