Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-08-07
2009-06-02
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
07543210
ABSTRACT:
A semiconductor device that includes a clock buffer, which generates an internal clock signal in response to a clock signal and a complementary clock signal if the semiconductor device is operating in a first mode and generates the internal clock signal in response to the clock signal and a reference voltage if the semiconductor device is operating in a second mode.
REFERENCES:
patent: 6069508 (2000-05-01), Takai
patent: 6239631 (2001-05-01), Fujioka et al.
patent: 6265918 (2001-07-01), Toda
patent: 6757212 (2004-06-01), Hamamoto et al.
patent: 2002/0016932 (2002-02-01), Kushiyama
patent: 2004/0190353 (2004-09-01), Kim et al.
patent: 2004/0260975 (2004-12-01), Nagura
patent: 11-273342 (1999-10-01), None
patent: 10-1999-0005916 (1999-01-01), None
patent: 10-2002-0043930 (2002-06-01), None
patent: 10-2002-0066478 (2002-08-01), None
Office Action for corresponding Korean Office Action No. 10-2005-0074493 dated Oct. 23, 2007.
Kim Joung-Yeal
Kim Sung-Hoon
Song Ho-Young
Harness & Dickey & Pierce P.L.C.
Samsung Electronics Co,. Ltd.
Ton David
LandOfFree
Semiconductor device and test system thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and test system thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and test system thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4067926