Semiconductor device and method of forming vertically offset...

Details Semiconductor device and method of forming vertically offset... Semiconductor device and method of forming vertically offset...

2010-03-09

2011-10-18

Lee, Cheung (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S107000, C438S110000, C438S614000, C257SE21499, C257SE21508, C257SE21510

Reexamination Certificate

active

08039384

ABSTRACT:
A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved by forming different height first and second conductive layer above a substrate. A first patterned photoresist layer is formed over the substrate. A first conductive layer is formed in the first patterned photoresist layer. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed over the substrate. A second conductive layer is formed in the second patterned photoresist layer. The height of the second conductive layer, for example 25 micrometers, is greater than the height of the first conductive layer which is 5 micrometers. The first and second conductive layers are interposed between each other close together to minimize pitch and increase I/O count while maintaining sufficient spacing to avoid electrical shorting after bump formation. An interconnect structure is formed over the first and second conductive layers.

REFERENCES:
patent: 7453156 (2008-11-01), Lee et al.
patent: 2007/0205520 (2007-09-01), Chou et al.
patent: 2007/0290345 (2007-12-01), Clevenger et al.
patent: 2009/0032932 (2009-02-01), Do et al.
patent: 2010/0044861 (2010-02-01), Chiu et al.
patent: 2010/0236822 (2010-09-01), Furutani et al.

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