4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Kevin William McCauley

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Analyzing CMOS circuit delay

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Random path delay testing methodology

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Self-timed AC CIO wrap method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Profile ID: LFUS-PAI-P-1566016

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