4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Pamela Sue Gillis

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Method and apparatus for initializing an integrated circuit...

Electronic digital logic circuitry – Multifunctional or programmable
Reexamination Certificate

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Scan-bypass architecture without additional external latches

Excavating
Patent

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Scan-bypass architecture without additional external latches

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Self-timed AC CIO wrap method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Profile ID: LFUS-PAI-P-1388469

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