Self aligned DMOS transistor and method of fabrication

Details Self aligned DMOS transistor and method of fabrication Self aligned DMOS transistor and method of fabrication

1998-02-18

2000-02-15

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438275, 438286, 438289, H01L 21336, H01L 218234

Patent

active

060252316

ABSTRACT:
A method for fabricating a self-aligned DMOS transistor is provided. The method includes forming a passivation layer (18, 68) on an oxide layer (16, 66) of a substrate (12, 56). The oxide layer (16, 66) is then removed from the surface of the substrate (12, 56) where it is exposed through the passivation layer (18, 68). A reduced surface field region (36, 74) is then formed where the surface of the substrate (12, 56) is exposed through the passivation layer (18, 68). An oxide layer (38, 80) is then formed on the reduced surface field region (36, 74).

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