Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-08-14
2010-10-19
Lebentritt, Michael S (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S446000, C438S448000, C438S649000, C438S721000, C438S744000, C257SE21165, C257SE21438, C257SE21507, C257SE21552, C257SE29127
Reexamination Certificate
active
07816218
ABSTRACT:
A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.
REFERENCES:
patent: 4873204 (1989-10-01), Wong et al.
patent: 5629230 (1997-05-01), Fazan et al.
patent: 6242354 (2001-06-01), Thomas
patent: 7078282 (2006-07-01), Chau et al.
patent: 2005/0151203 (2005-07-01), Cho et al.
patent: 2007/0254442 (2007-11-01), Manger et al.
patent: 2008/0116481 (2008-05-01), Sharma et al.
patent: 2008/0160709 (2008-07-01), Chen et al.
patent: 2008/0258245 (2008-10-01), Forbes et al.
King Sean
Klaus Jason
Rachmady Willy
Greaves John N.
Intel Corporation
Lebentritt Michael S
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