Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Inventor
active
Analyzing CMOS circuit delay
Apparatus and method for testing high speed components using low
Method and apparatus for testing path delays in a high-speed...
Method and system for performing non-standard insitu burn-in tes
Scanable latch circuit and method for providing a scan...
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Profile ID: LFUS-PAI-P-169064