Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Inventor
active
Design-For-testability planner
Distributed test compression for integrated circuits
Method and apparatus to use physical design information to...
Method and mechanism for implementing electronic designs...
Scan testing architectures for power-shutoff aware systems
No associations
LandOfFree
Vivek Chickermane does not yet have a rating. At this time, there are no reviews or comments for this inventor.
If you have personal experience with Vivek Chickermane, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vivek Chickermane will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-P-2180459