Scan flip-flop circuit with reduced power consumption

Details Scan flip-flop circuit with reduced power consumption Scan flip-flop circuit with reduced power consumption

2007-06-12

2007-06-12

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

11068908

ABSTRACT:
A scan flip-flop circuit and related scan chain are disclosed. The scan flip flop comprises in one embodiment an input stage receiving, selecting between, and outputting either a normal logic signal or a scan logic signal in accordance with an operation mode for the scan flip-flop circuit. The scan flip-flop further comprises a flip-flop receiving either the normal logic signal or the scan logic signal selected by the input stage, and outputting in accordance with a clock signal a first logic signal from a first flip-flop output terminal and an output stage receiving the first logic signal and comprising first and second output terminals, such that a signal output from the first output terminal is identical to the normal logic signal received in the input stage, and a signal output from the second output terminal maintains a high logic value when the scan flip-flop circuit operates in a normal mode and a signal output from the first and second output terminals are identical to the scan logic signal received in the input stage when the scan flip-flop circuit operates in a scan mode.

REFERENCES:
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patent: 6794898 (2004-09-01), Komaki
patent: 2001-305180 (2001-10-01), None
patent: 2002-311092 (2002-10-01), None

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