Scan cell systems and methods

Details Scan cell systems and methods Scan cell systems and methods

2002-12-23

2004-11-09

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S093000, C714S726000

Reexamination Certificate

active

06815977

ABSTRACT:

BACKGROUND
A conventional integrated circuit (IC) may include millions of logic gates. Each of these logic gates must be properly fabricated in order for the IC to operate as designed. Testing techniques have therefore been developed to ensure that the logic gates of an IC have been properly fabricated and that the gates provide proper functioning to the IC.
Some testing techniques utilize scan circuits that are built into an IC exclusively for testing purposes. An IC may include many functional logic circuits separated by associated state elements. A state element stores values that are produced by its associated logic circuit under the control of a system clock. Scan circuits are coupled to these state elements so as to store test data, or scan values, directly into the state elements and to read out values stored by the state elements.
In operation, scan values are determined using Automatic Test Pattern Generation (ATPG) techniques or the like. These values are stored into state elements that are associated with functional logic circuits to be tested. The system clock is activated for a predetermined amount of cycles based on the test being performed so as to allow the stored values to propagate through the functional logic. Next, the scan circuits are controlled so as to capture values that are stored in state elements of interest. The captured values may then be compared with expected values to determine whether the functional logic circuits operated properly.
Scan circuits have conventionally been used in conjunction with static functional circuits. These static circuits include traditional static complementary metal-oxide semiconductor (CMOS) logic, flip-flops and latches. However, ICs often include other types of functional circuits. One such circuit type is the Domino circuit. A Domino circuit is a dynamic circuit that is pre-charged and evaluated rather than traditionally clocked. Domino circuits often provide speed advantages over static circuits but may require more die space than a corresponding static circuit. As a result, Domino circuits are often used to provide functions for which speed is of primary importance.
FIG. 1
illustrates a set-dominant latch (SDL) used in some Domino circuits. SDL
1
is a state element of a Domino circuit and therefore provides functionality similar to a state element of a static circuit. Generally, SDL
1
latches a data value present on the Data signal line in response to an active Clk signal. As a result, the latched data value is present on output signal line Q. The data value that is present on the Data signal line is usually generated by functional logic associated with SDL
1
.
Scan circuits used in conjunction with static functional logic circuits are not suitable for Domino-based functional logic circuits. As a result, functional patterns are conventionally used to test Domino circuits. More specifically, data values are applied to the input pins of an IC under test and allowed to propagate through the IC. Output pins are then examined to determine whether the data values propagated properly. Testing using functional patterns is often much less efficient and effective than scan-based testing using ATPG scan values.
Scan values may be input to an IC by automatic test equipment (ATE). The I/O speed of such test equipment is not suitable for use in conjunction with many modern ICs, including microprocessors and application-specific ICs. ATE I/O speeds therefore result in long test times that increase as the amount of test data increases. The test speed is limited to the ATE I/O speed even if (as is usually the case) an IC under test is capable of processing the test data at much higher speeds. The long test times limit the number of ICs that can be tested in a given period and thereby limit IC production throughput.
Scan circuits offer efficient and effective testing at the expense of IC die area. Accordingly, it is desirable to reduce a size of current scan circuits while still maintaining their functionality. One useful type of conventional scan circuit is illustrated in FIG.
2
. Hold scan circuit
10
provides the functionality described above with respect to other scan circuits and also provides independence between the scan path and the functional logic path. Consequently, hold scan circuit
10
may store a value in state element
15
while functional logic associated with state element
15
is being clocked. Hold scan circuit
10
may also capture a value stored in state element
15
at any time while the functional logic is being clocked. Despite these features, hold scan circuit
10
is often unsuitable for particular applications because of the significant amount of IC die space required by its elements.


REFERENCES:
patent: 5898330 (1999-04-01), Klass
patent: 5978944 (1999-11-01), Parvathala et al.
patent: 6560737 (2003-05-01), Colon-Bonet et al.

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