Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-10-18
2005-10-18
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S710000, C714S718000, C365S201000
Reexamination Certificate
active
06957372
ABSTRACT:
An integrated circuit having a DRAM array connected to a power supply is tested for excessive current draw by selectively applying voltage to a single wordline or bitline, measuring current drawn, comparing the result with a reference number representing acceptable leakage, and replacing columns of the array having excessive leakage, thereby identifying and repairing latent defects that may become a cause of failure.
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Barth, Jr. John Edward
Parries Paul Christian
Robson Norman Whitelaw
Blecker Ira D.
Infineon - Technologies AG
International Business Machines - Corporation
Tu Christine T.
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