Reactive Ion Etching chamber design for flip chip...

Details Reactive Ion Etching chamber design for flip chip... Reactive Ion Etching chamber design for flip chip...

2000-06-22

2003-03-11

Gulakowski, Randy (Department: 1746)

Etching a substrate: processes

Gas phase etching of substrate

Application of energy to the gaseous etchant or to the...

C216S070000, C438S009000, C438S707000, C438S710000, C204S298070, C204S298080, C204S298110, C204S298310, C156S345420, C118S7230AN

Reexamination Certificate

active

06531069

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to reactive ion chambers and methods of operation thereof and more particularly to a method and apparatus for overcoming nonuniformity of etching in the presence of tall structures on a substrate.
2. Description of Related Art
FIG. 1A
shows a schematic diagram of a vertical elevation of one type of conventional Prior Art RIE (Reactive Ion Etching) system which is housed in a RIE etching chamber C and which is used to remove a film from the exposed surface of a workpiece such as silicon semiconductor wafer W. There is a inlet flow IF of etching gases supplied to inlet GI to the by RIE chamber C. At the top of chamber C, a gas input line GI supplies that inlet flow IF of fresh reactive gases to the top center of the inlet manifold IM of a gas-shower head SH. The gas-shower head SH comprises an inlet manifold IM and a combined ventilator and metallic upper electrode UE with an array of widely and evenly dispersed, parallel, vertical vent holes VH therethrough. Thus, the reactive etching gases IF are fairly uniformly dispersed at the outlets of the vent holes. VH in the gas-shower bead SH. The vent holes VH communicate between the inlet manifold IM and an ionization space IS within the chamber C between the upper electrode UE and a disk-shaped lower electrode LE, upon which the wafer W is supported. The disk-shaped lower electrode LE has an upright vertical axis parallel to the vertical axis of the chamber C. The upper electrode UE and lower electrode LE are energized by application thereto of RF electrical power (applied to the bottom lower electrode LE, or the lower electrode LE and upper electrode UE both). When the upper and the lower electrodes UE and LE are energized, in the presence of an appropriate pressure/flow rate combination the electrodes UE and LE generate a plasma, i.e. ionize the reactive etching gases IF. The plasma exists between the upper electrode UE and the lower electrode LE, which causes selective etching by chemical reactions between the etching gases in the plasma and an unwanted layer of material on the surface of wafer W. The etching process removes that unwanted layer on the surface of the wafer W in a selective process In other words, the plasma interacts with the unwanted film on the top surface of the wafer W to remove that film. To continue the etching process to completion, a constant supply of etching gases IF must enter gas inlet GI and pass through the manifold, IM and the upper electrode US and vent holes VH into the ionization space IS in the RIE etching chamber C. To that end the outflowing gases OF which have been produced by the etching process arc exhausted from the ionization space IS though exhaust holes EH in a gas outlet plate OP below the lower electrode LE. The exhaust holes EH are located on a larger radius from the center of the lower electrode LE. Two outlet gas flow paths OF are shown to the two exhaust holes EH in the gas outlet plate OP in FIG.
1
A. Below the gas outlet plate OP is an outlet manifold OM connected to a main gas outlet GO from which the exhaust gases EF are removed by a pump (not shown).
FIG. 1B
shows a schematic, plan view of the configuration of the outlet plate OP of
FIG. 1A
with a 360° ring of exhaust holes EH extending vertically therethrough from top to bottom. The exhaust holes EH through the gas outlet plate OP are located just beyond the periphery of the wafer W. In the chamber C, the gas pressure is maintained low enough so that it is approximately correct to show a straight line, radial flow of ionized species from center to edge of the wafer W. These flow paths are based upon the path the average ions or molecules in the mass of the gases which pass through the ionization space IS from a single hypothetical vent hole VH (now shown) to give an overall impression of the linear flow from vent holes VH to exhaust holes EH. Because of random motion caused by molecular and ionic collisions some scattering of molecules and ions occurs but the arrows are indicative of the overall average, linear motion of ions and molecules from vent holes VH to exhaust holes EH.
FIG. 1C
is an enlarged, fragmentary, schematic, plan view of a single exhaust hole EH with arrows showing a number of flow paths FP for the etching gases approaching a single exhaust hole EH. The arrows indicate a number of straight line paths to that exhaust hole EH which originated at a number of vent holes VH (not shown).
In the configuration of
FIGS. 1A and 1B
, the ionized gaseous species run, i.e flow, directly from all over the wafer surface to the nearest edge of the wafer W, forming a plurality radial paths of the ionized gaseous species as indicated by FIG.
1
C. The flux of the ions is minimum at the center and maximum near the edge. The etch rate is minimum at the center and maximum near the edge. In the absence of any tall (100 micron) feature on the wafer surface, this etch rate non-uniformity can be easily controlled within one sigma (&Sgr;) of 10%.
In the presence of the flip chip interconnection features like tall (100 micron) solder bumps or any relatively tall features, the flow of the ionized gaseous species on the surface of the wafer is obstructed by each of the such tall features such as solder bump SB shown on wafer W in FIG.
2
A and an ion path IP
1
hypothetically followed by an ion travelling along a straight line just missing interception by the upper edge of the solder bump SB from a point source, i.e. a vent hole VH in FIG.
1
A. Therefore, each of such flip chip interconnection features forms a number of overlapping shadows SA (extending radially on the surface of wafer W towards the edge) where reduced or even minimal interaction occurs with the top layer film to be etched, resulting in very little etching deep within the exemplary shadow region SR shown formed in the shadow area SA on the surface of wafer W in FIG.
2
A. Experimental data has shown that irrespective of the extent of overetching applied, feature shadows remain in the areas of minimal etching.
FIG. 2B
shows a plan view of
FIG. 2A
showing that with two linear ion paths IP
1
and IP
2
, the shadows SA are widest and least accessible near the bottom of the “shaded” or leeward side of the solder bump SB.
U.S. Pat. No. 5,980,687, of Koshimizu for “Plasma Processing Apparatus Comprising a Compensating-Process-Gas Supply Means in Synchronism with a Rotating Magnetic Field” teaches use of a compensating rotating process gas inlet assembly with the rotation of the magnetic field generated by an assembly of magnets. The Koshimizu patent indicates that with the arrangement shown therein a more uniform plasma is generated leading to uniform etching. That is a method appropriate for use when surface to be etched is substantially nearly flat.
U.S. Pat. No. 6,014,943 of Arami et al. for “Plasma Process Device” describes dipole ring magnet apparatus surrounding a plasma generating chamber.
U.S. Pat. No. 5,834,730, of Suzuki et al. for “Plasma Processing Equipment and Gas Discharging Device” describes a system which includes a gas discharging device which enables CVD (Chemical Vapor Deposition) film deposition in a multiple chamber set up. The Suzuki et al. patent also describes use of the same gas discharging device in multiple chamber RIE setup.
U.S. Pat. No. 5,766,498 of Kojima et al. for “Anisotropic Etching Method and Apparatus” describes improving planar RIE uniformity by creating temperature gradient in a gas-shower head and making the gas-shower head larger than the size of the wafer.
U.S. Pat. No. 5,110,437 of Yamada et al. for “Processing Apparatus” describes an arrangement which allows up and down movement of the process gas inlet and outlet pipes. The patent indicates that the method described therein would allow a user to employ more process chamber variables to optimize the RIE process.
U.S. Pat. No. 5,009,738, dated Apr. 23, 1991 of Gruenwald et al. for “Apparatus for Plasma Etching” describes a chamber design allowing a fixed set of selectable outlet holes in a stat

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