Random access memory of a CSL system with a bit line pair and an

Details Random access memory of a CSL system with a bit line pair and an Random access memory of a CSL system with a bit line pair and an

1996-06-13

1999-01-05

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Precharge

36518911, 36523003, G11C 700

Patent

active

RE0360279

ABSTRACT:
In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

REFERENCES:
patent: 4112512 (1978-09-01), Arzubi et al.
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patent: 4780852 (1988-10-01), Kajigaya et al.
patent: 4926384 (1990-05-01), Roy
patent: 4996671 (1991-02-01), Suzuki et al.
patent: 5047984 (1991-09-01), Monden
"An Experimental 1Mb DRAM With On-Chip Voltage Limiter", Itoh, K. et al., Digest of Technical Papers, IEEE International Solid-State Circuits Conference, Feb., 1984, p. 282.

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