Programmable test for memories

Details Programmable test for memories Programmable test for memories

2006-08-15

2006-08-15

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S819000

Reexamination Certificate

active

07093176

ABSTRACT:
A programmable built in self test, BIST, system for testing a memory, comprises an instruction register formed in the same chip as the memory; a circuit for loading the register by successive instructions, each instruction comprising at least one address control field, a first number (m) of operation fields, a number-of-operations field specifying a second number t+1, with t+1≦m; a circuit controlled by the address control field to determine successive addresses; and a cycle controller for executing, for each successive address, the second number (t+1) of successive operations, each of which is determined by one of the t+1 first operation fields.

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