Process for manufacturing silicon epitaxial wafer

Details Process for manufacturing silicon epitaxial wafer Process for manufacturing silicon epitaxial wafer

2002-01-04

2003-04-08

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S476000, C438S511000, C438S769000

Reexamination Certificate

active

06544899

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a process capable of manufacturing an epitaxial wafer which exerts a stable IG capability without being affected by a thermal history of a substrate for epitaxial growth and has the IG capability excellent from an early stage of a device process.
BACKGROUND ART
In a silicon wafer prepared using a silicon single crystal grown by a Czochralski (CZ) method, interstitial oxygen is included as an impurity at a concentration of the order ranging from 5×10
17
to 10×10
17
atoms/cm
3
. The interstitial oxygen is supersaturated in a period of a thermal history from solidification of a grown crystal until the crystal being cooled to room temperature in a pulling operation (hereinafter referred to as a crystal thermal history) so that the interstitial oxygen precipitates to form oxygen precipitation nuclei (microprecipitates of silicon oxides).
When the silicon wafer is subjected to heat treatment in a process for fabricating a semiconductor integrated circuit, the oxygen precipitation nuclei are grown to progress oxygen precipitation, with the result that there are generated oxide precipitates and micro-defects such as dislocations caused thereby. The oxide precipitates existing in a device active layer of the wafer surface deteriorate device characteristics, while those in the interior of the wafer work effectively as sites capturing heavy metal impurities to exert an effect called IG (Internal Gettering), the device characteristics and a yield of the devices being improved. From this viewpoint, control of oxygen precipitation in a CZ wafer is an important issue and researches thereon have extensively been conducted for a long time.
In order to make it defect-free a device formation region in the vicinity of the wafer surface, there is sometimes used an epitaxial wafer (hereinafter also simply referred to as an epi-wafer) prepared by depositing a silicon single crystal layer (hereinafter also simply referred to as an epitaxial layer or an epi-layer) on a CZ wafer in vapor phase growth. In this epi-wafer as well, it is important that an IG capability is added to a substrate thereof.
However, when ordinary epitaxial growth is performed at a high temperature of 1000° C. or higher, oxygen precipitation nuclei that have been formed in a crystal thermal history of pulling a silicon single crystal from which an epitaxial growth substrate is obtained become solid solutions, oxygen precipitation being suppressed in a device fabrication process compared with an ordinary CZ silicon wafer not heat-treated. Therefore, reduction of an IG capability in an epi-wafer becomes a problem.
As measures to solve this problem, there is a process in which a substrate is subjected to heat treatment at a temperature on the order of 800° C. prior to an epitaxial process to grow oxygen precipitation nuclei to a large size with the result that the oxygen precipitation nuclei are not annihilated even in an epitaxial process at a high temperature (for example, see JP A 98-223641), a process, as described in Japanese Patent Application No. 2000-17479 filed by the present applicant, in which oxygen precipitation nuclei are reproduced by heat treatment at a temperature on the order of 450 to 750° C. after an epitaxial process, and other processes.
However, since the process in which the substrate is subjected to heat treatment prior to the epitaxial process utilizes oxygen precipitation nuclei formed in a crystal thermal history, a density of oxygen precipitation nuclei differs depending on a crystal thermal history of a wafer; therefore, a density of oxide precipitates varies according to differences in conditions for pulling a crystal or in crystal positions, so there arises a problem that a stable gettering capability is not attained. Further, oxygen precipitation is inherently hard to proceed in an N
+
substrate doped with Sb (antimony) or As (arsenic) at a high concentration (a silicon wafer having a conductivity type of n-type and resistivity of 0.1 &OHgr;·cm or lower) so that a density of oxygen precipitation nuclei formed in a crystal thermal history is low to make an effect of heat treatment prior to an epitaxial process almost nothing.
Furthermore, since formation of oxygen precipitation nuclei in the N
+
substrate is hard to proceed even in heat treatment after an epitaxial process, a problem again arises that a long heat treatment time is required to attain a sufficiently high density. As for a reason why oxygen precipitation is hard to proceed in the N
+
substrate, several models thereon have already been proposed, but it is not as yet clear, so descriptions thereon is not provided here.
On the other hand, an N/N
+
epitaxial wafer using an N
+
substrate (an epi-wafer prepared by growing an n-type epitaxial layer having resistivity of 0.1 &OHgr;·cm or higher on an N
+
substrate) is regarded as promising materials for CCD from a structural viewpoint. However, an IG effect cannot be expected therefrom as described above; an N/N epi-wafer (an epitaxial wafer prepared by growing an n-type epitaxial layer having resistivity of 0.1 &OHgr;·cm or higher on an n-type substrate having resistivity of 0.1 &OHgr;·cm or higher) is widely used instead thereof In this case as well, in order to add an IG effect, heat treatment for oxygen precipitation is required before or after an epitaxial process. In consideration of such circumstances, it is an important problem to add an IG effect to an N/N
+
epi-wafer with a relatively simple and easy way.
As a simple and convenient method to accelerate oxygen precipitation, there is available rapid heating and rapid cooling heat treatment called RTA (Rapid Thermal Annealing) (see JP A 94-504878, for example). In many cases, a heat treatment apparatus capable of performing this type of heat treatment (an RTA apparatus) adopts a lamp heating system, in which heat treatment can be realized at a temperature increase/decrease rate on the order of 10 to 100° C./sec.
Excess vacancies introduced from a wafer surface in the RTA process are considered to facilitate oxygen precipitation. However, it has been understood that the precipitation acceleration effect is cancelled by performing an epitaxial process immediately after the RTA. This is imagined because vacancies outdiffuse in the epitaxial process. While the oxygen precipitation effect further increases in heat treatment at a temperature on the order of 450° C. to 800° C. after the RTA, no sufficient growth of oxide precipitates is achieved due to the low heat treatment temperature and the oxide precipitates cannot survive in a high temperature epitaxial process. Especially, an N
+
substrate in which oxygen precipitation is hard to occur is greatly affected thereby.
A low temperature device process introduced in recent years suppresses growth of oxide precipitates, so there is a fear that a sufficient gettering capability is not secured. Therefore, it is preferable that oxide precipitates having a large size to a detectable level are formed at a stage prior to a device process. In a prior art process, however, it was hard to form oxide precipitates having a detectable size immediately after an epitaxial process.
DISCLOSURE OF THE INVENTION
It is an object of the present invention to provide a process for manufacturing a silicon epitaxial wafer capable of manufacturing an epitaxial wafer, which exerts a stable IG capability without being affected by a thermal history of a substrate for epitaxial growth and has the IG capability excellent from an early stage of a device process, and particularly, canceling an IG shortage in an N/N
+
epitaxial wafer caused by a problem that oxygen precipitation is hard to proceed in an N
+
substrate with a simple and easy way.
In order to solve the above problem, a process for manufacturing a silicon epitaxial wafer of the present invention comprises the steps of: performing RTA (rapid heating and rapid cooling heat treatment) at a temperature of 1200° C. to 1350° C. for 1 to 120 seconds

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