Process for integrating stacked capacitor DRAM devices with MOSF

Details Process for integrating stacked capacitor DRAM devices with MOSF Process for integrating stacked capacitor DRAM devices with MOSF

1997-09-19

1998-12-01

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438241, H01L 218242

Patent

active

058438173

ABSTRACT:
A semiconductor fabrication process has been developed in which both stacked capacitor DRAM, and MOSFET logic device structures, are integrated on a single silicon chip. The process features combining process steps for both device types. A single dielectric layer is used as a capacitor dielectric layer, for a stacked capacitor DRAM device, and as a gate insulator layer for a MOSFET logic device. In addition a specific polysilicon layer is used for formation of the upper polysilicon electrode, for the stacked capacitor DRAM device, as well as use for formation of the polysilicon gate structure, for the MOSFET logic device. A specific anneal cycle is used to reduce charges in the stacked capacitor DRAM device, while a less severe anneal cycle is used with the shallow junction MOSFET logic device.

REFERENCES:
patent: 5066602 (1991-11-01), Takemoto et al.
patent: 5340762 (1994-08-01), Vora
patent: 5481493 (1996-01-01), Bergemont
patent: 5521110 (1996-05-01), Gill
patent: 5570314 (1996-10-01), Gill
patent: 5585292 (1996-12-01), Morita et al.
patent: 5668035 (1997-09-01), Fang et al.
patent: 5719079 (1998-02-01), Yoo et al.
patent: 5759889 (1998-06-01), Sakao

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