Process for fabricating semiconductor memory device with...

Details Process for fabricating semiconductor memory device with... Process for fabricating semiconductor memory device with...

1997-03-25

2001-02-20

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S637000, C438S792000, C438S970000, C257S315000, C257S650000

Reexamination Certificate

active

06190966

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a process for fabricating a semiconductor memory device with high data retention including a silicon nitride etch stop layer formed at high temperature with a low hydrogen ion concentration.
2. Description of the Related Art
A flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) semiconductor memory includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block.
Tungsten damascene is a process for fabricating local interconnects which can be advantageously applied to semiconductor devices including flash EEPROMs. The process includes forming an insulator layer of, for example, tetraethylorthosilicate (TEOS) glass over the memory cells, and using Reactive Ion Etching (RIE) to form vertical interconnect holes through the glass down to interconnect areas (source, drain, etc.) of the cells. The holes are filled with tungsten which ohmically contacts the interconnect areas to form the local interconnects.
The TEOS etch is conventionally performed using octafluorobutene (C
4
F
8
) etchant, which also has a high etch rate for silicon. For this reason, a mechanism must be provided for performing the TEOS etch without allowing the etchant to act on the silicon of the underlying interconnect areas.
Such a mechanism includes forming a silicon nitride etch stop layer underneath the TEOS layer, and performing the etch in two stages. The first stage is the octafluorobutene etch through the TEOS layer, which terminates at the etch stop layer since octafluorobutene has a low etch rate for silicon nitride.
Then, a second RIE etch is performed using fluoromethane (CH
3
F), which forms holes through the portions of the etch stop layer that are exposed through the holes in the TEOS layer, down to the interconnect areas of the devices. This is possible because fluoromethane has a high etch rate for silicon nitride, but a low etch rate for TEOS.
The structure can be further facilitated by using a silicide technique to increase the conductivity of the interconnect areas of the cells. Siliciding is a fabrication technique that enables electrical interconnections to be made that have reduced resistance and capacitance.
The silicide process comprises forming a layer of a refractory metal silicide material such as tungsten, titanium, tantalum, molybdenum, etc. on a silicon interconnect area (source or drain diffusion region) or on a polysilicon gate to which ohmic contact is to be made, and then reacting the silicide material with the underlaying silicon material to form a silicide surface layer having much lower resistance than heavily doped silicon or polysilicon. A silicide surface layer formed on a polysilicon gate is called “polycide”, whereas a silicide surface layer formed on silicon using a self-aligned process is called “salicide”.
A problem which has remained unsolved in the fabrication of flash EEPROM memories and other semiconductor device structures is data retention. A flash EEPROM cell is programmed by creating a negative charge (electrons) on the floating gate. The charge should remain until it is deliberately removed by erasing the cell.
However, the charge on a conventional flash EEPROM cell which is fabricated using a silicon nitride etch stop layer that is conventionally formed at a temperature of approximately 350° C. has been found to decrease substantially with time. This problem has remained unsolved in the art.
SUMMARY OF THE INVENTION
The present invention overcomes the drawbacks of the prior art by overcoming the problem of unsatisfactory data retention in semiconductor devices such as flash EEPROMs which include silicon nitride etch stop layers.
In accordance with the present invention, a semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention.
A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480° C. such that the etch stop layer has a very low concentration of hydrogen ions.
The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.
These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.


REFERENCES:
patent: 4854263 (1989-08-01), Chang et al.
patent: 5068201 (1991-11-01), Spinner, III et al.
patent: 5094967 (1992-03-01), Shinada et al.
patent: 5264724 (1993-11-01), Brown et al.
patent: 5294558 (1994-03-01), Subbanna
patent: 5515323 (1996-05-01), Yamazaki et al.
patent: 5681425 (1997-10-01), Chen
patent: 5731238 (1998-03-01), Cavins et al.
patent: 5731242 (1998-03-01), Parat et al.
patent: 5795820 (1996-07-01), Kepler
patent: 5825068 (1997-03-01), Yang
patent: 5840624 (1998-11-01), Jang et al.
patent: 6087254 (2000-07-01), Pan et al.
R.C. Sun, J. T. Clemens and J. T. Nelson, “Effects of Silicon Nitride Encapsulation On MOS Device Stability, ” Proc. IRPS, pp. 244-251 (1980).
J. Givens et al., “A Low Temperature Local Interconnect Process In A 0.25 &mgr;m Channel CMOS Logic Technology With Shallow Trench Isolation, ” Proc. VMIC, pp. 43-48 (1994).
Stanley Wolf, Ph.D. and Richard N. Tauber, Ph.D.,Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, California, 1986, pp. 191-194.

Affiliated with

Also associated with

Rating

Process for fabricating semiconductor memory device with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating semiconductor memory device with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating semiconductor memory device with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2563239