Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-03-29
2005-03-29
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S724000, C438S722000, C438S725000, C438S745000, C438S757000
Reexamination Certificate
active
06872665
ABSTRACT:
A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.
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Celii Francis G.
Kraft Robert
McKerrow Andrew
Newton Kenneth J.
Ralston Andrew
Brady III W. James
Garner Jacqueline J.
Kunemund Robert
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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