Poly open polish process

Details Poly open polish process Poly open polish process

2007-01-23

2007-01-23

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S194000, C438S529000, C438S626000, C257SE21443, C257SE21444

Reexamination Certificate

active

11015151

ABSTRACT:
A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used relative to an etch stop layer abutting a transistor gate. This allows the first CMP step to stop after contacting the etch stop layer, which results in substantially uniform “within die”, “within wafer”, and “wafer to wafer” topography. The removal step may expose a temporary component, such as a polysilicon gate within the transistor gate structure. Once the polysilicon gate is exposed other processes may be employed to produce a transistor gate having desired properties.

REFERENCES:
patent: 5891784 (1999-04-01), Cheung et al.
patent: 6248667 (2001-06-01), Kim et al.
patent: 6743683 (2004-06-01), Barns et al.
patent: 2001/0004542 (2001-06-01), Woerlee et al.

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