4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Ishwardutt Parulkar

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Boundary scan cell architecture with complete set of...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Boundary scan cell design for high performance I/O cells

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method for operating a boundary scan cell design for high...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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On-chip testing of embedded memories using Address Space...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Plesiochronous transmit pin with synchronous mode for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Profile ID: LFUS-PAI-P-2599814

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