PFET with tailored dielectric and related methods and...

Details PFET with tailored dielectric and related methods and... PFET with tailored dielectric and related methods and...

2007-12-13

2011-11-08

Le, Thao (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S224000, C257S371000, C257SE21632, C257SE21639

Reexamination Certificate

active

08053306

ABSTRACT:
A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.

REFERENCES:
patent: 6787413 (2004-09-01), Ahn et al.
patent: 2002/0025626 (2002-02-01), Hattangady et al.
patent: 2005/0051828 (2005-03-01), Park et al.
patent: 2006/0030096 (2006-02-01), Weimer
patent: 2006/0094183 (2006-05-01), Wieczorek et al.
patent: 2006/0172480 (2006-08-01), Wang et al.
patent: 2007/0178634 (2007-08-01), Jung et al.

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