Package design and method of manufacture for chip grid array

Details Package design and method of manufacture for chip grid array Package design and method of manufacture for chip grid array

2005-05-12

2008-11-25

Smith, Matthew S. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S738000, C257SE21499, C257SE23061

Reexamination Certificate

active

07456496

ABSTRACT:
A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.

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