Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-02-02
2009-06-02
Jackson, Jr., Jerome (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000, C438S270000, C438S287000, C438S591000, C257S324000, C257SE21679
Reexamination Certificate
active
07541242
ABSTRACT:
An array of memory cells configured to store at least one bit per one F2includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
REFERENCES:
patent: 4184207 (1980-01-01), McElroy
patent: 4420504 (1983-12-01), Cooper
patent: 4755864 (1988-07-01), Ariizumi
patent: 4881114 (1989-11-01), Mohsen
patent: 5241496 (1993-08-01), Lowrey
patent: 5330930 (1994-07-01), Chi
patent: 5341328 (1994-08-01), Ovshinsky
patent: 5378647 (1995-01-01), Hong
patent: 5379253 (1995-01-01), Bergemont
patent: 5397725 (1995-03-01), Wolstenholme
patent: 5406509 (1995-04-01), Ovshinsky
patent: 5467305 (1995-11-01), Bertin
patent: 5576236 (1996-11-01), Chang
patent: 5610099 (1997-03-01), Stevens
patent: 5617351 (1997-04-01), Bertin
patent: 5768192 (1998-06-01), Eitan
patent: 5792697 (1998-08-01), Wen
patent: 5858841 (1999-01-01), Hsu
patent: 5892710 (1999-04-01), Fazio
patent: 5911106 (1999-06-01), Tasaka
patent: 5936274 (1999-08-01), Forbes
patent: 5946558 (1999-08-01), Hsu
patent: 5966603 (1999-10-01), Eitan
patent: 5973356 (1999-10-01), Noble
patent: 5990509 (1999-11-01), Burns
patent: 5991225 (1999-11-01), Forbes
patent: 5994745 (1999-11-01), Hong
patent: 6011725 (2000-01-01), Eitan
patent: 6028342 (2000-02-01), Chang
patent: 6030871 (2000-02-01), Eitan
patent: 6044022 (2000-03-01), Nachumovsky
patent: 6072209 (2000-06-01), Noble
patent: 6081456 (2000-06-01), Dadashev
patent: 6093606 (2000-07-01), Lin
patent: 6108240 (2000-08-01), Lavi
patent: 6114725 (2000-09-01), Furukawa
patent: 6124729 (2000-09-01), Noble
patent: 6133102 (2000-10-01), Wu
patent: 6134156 (2000-10-01), Eitan
patent: 6144093 (2000-11-01), Davis
patent: 6147904 (2000-11-01), Liron
patent: 6150687 (2000-11-01), Noble
patent: 6157570 (2000-12-01), Nachumovsky
patent: 6172396 (2001-01-01), Chang
patent: 6174758 (2001-01-01), Nachumovsky
patent: 6175523 (2001-01-01), Yang
patent: 6181597 (2001-01-01), Nachumovsky
patent: 6184089 (2001-02-01), Chang
patent: 6201282 (2001-03-01), Eitan
patent: 6201737 (2001-03-01), Hollmer
patent: 6204529 (2001-03-01), Lung
patent: 6207504 (2001-03-01), Hsieh
patent: 6208557 (2001-03-01), Bergemont
patent: 6215702 (2001-04-01), Derhacobian
patent: 6218695 (2001-04-01), Nachumovsky
patent: 6222768 (2001-04-01), Hollmer
patent: 6240020 (2001-05-01), Yang
patent: 6243300 (2001-06-01), Sunkavalli
patent: 6251731 (2001-06-01), Wu
patent: 6255166 (2001-07-01), Ogura
patent: 6256231 (2001-07-01), Lavi
patent: 6266281 (2001-07-01), Derhacobian
patent: 6269023 (2001-07-01), Derhacobian
patent: 6272043 (2001-08-01), Hollmer
patent: 6275414 (2001-08-01), Randolph
patent: 6282118 (2001-08-01), Lung
patent: 6291854 (2001-09-01), Peng
patent: 6297096 (2001-10-01), Boaz
patent: 6303436 (2001-10-01), Sung
patent: 6303479 (2001-10-01), Snyder
patent: 6320223 (2001-11-01), Hueting
patent: 6327174 (2001-12-01), Jung
patent: 6331467 (2001-12-01), Brown
patent: 6348711 (2002-02-01), Eitan
patent: 6392930 (2002-05-01), Jung
patent: 6417053 (2002-07-01), Kuo
patent: 6421275 (2002-07-01), Chen
patent: 6429063 (2002-08-01), Eitan
patent: 6432778 (2002-08-01), Lai
patent: 6461949 (2002-10-01), Chang
patent: 6468864 (2002-10-01), Sung
patent: 6469342 (2002-10-01), Kuo
patent: 6477084 (2002-11-01), Eitan
patent: 6486028 (2002-11-01), Chang
patent: 6487050 (2002-11-01), Liu
patent: 6498377 (2002-12-01), Lin
patent: 6514831 (2003-02-01), Liu
patent: 6531887 (2003-03-01), Sun
patent: 6541815 (2003-04-01), Mandelman
patent: 6545309 (2003-04-01), Kuo
patent: 6552387 (2003-04-01), Eitan
patent: 6559013 (2003-05-01), Pan
patent: 6576511 (2003-06-01), Pan
patent: 6580135 (2003-06-01), Chen
patent: 6580630 (2003-06-01), Liu
patent: 6602805 (2003-08-01), Chang
patent: 6607957 (2003-08-01), Fan
patent: 6610586 (2003-08-01), Liu
patent: 6613632 (2003-09-01), Liu
patent: 6617204 (2003-09-01), Sung
patent: 6660590 (2003-12-01), Yoo
patent: 6670246 (2003-12-01), Hsiao
patent: 6768166 (2004-07-01), Hagemeyer
patent: 6853587 (2005-02-01), Forbes
patent: 6885060 (2005-04-01), Nomoto et al.
patent: 7067875 (2006-06-01), Shukuri
patent: 2001/0001075 (2001-05-01), Ngo
patent: 2001/0004332 (2001-06-01), Eitan
patent: 2001/0011755 (2001-08-01), Tasaka
patent: 2002/0142569 (2002-10-01), Chang
patent: 2002/0146885 (2002-10-01), Chen
patent: 2002/0151138 (2002-10-01), Liu
patent: 2002/0177275 (2002-11-01), Liu
patent: 2002/0182829 (2002-12-01), Chen
patent: 2003/0057997 (2003-03-01), Sun
patent: 2003/0067807 (2003-04-01), Lin
patent: 2003/0117861 (2003-06-01), Maayan
patent: 2003/0235075 (2003-12-01), Forbes
patent: 2003/0235076 (2003-12-01), Forbes
patent: 2004/0004859 (2004-01-01), Forbes et al.
patent: 2004/0031984 (2004-02-01), Kianian
patent: 2004/0041176 (2004-03-01), Prall
patent: 2004/0066672 (2004-04-01), Forbes
patent: 10219917 (2003-11-01), None
patent: 84303740.9 (1985-01-01), None
patent: 90115805.5 (1991-02-01), None
patent: 01113179.4 (2002-12-01), None
B. Eitan et al., “Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM™ Device,” IEEE Electron Device Lett., vol. 22, No. 11, (Nov. 2001) pp. 556-558, Copyright 2001 IEEE.
B. Eitan et al., “Spatial Characterization of Hot Carriers Injected into the Gate Dielectric Stack of a MOFSET Based on Non-Volatile Memory Device,” date unknown, pp. 58-60.
B. Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett, vol. 21, No. 11, (Nov. 2000), pp. 543-545, Copyright 2000 IEEE.
E. Maayan et al., “A 512Mb NROM Flash Data Storage Memory with 8MB/s Data Range,” Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, (Feb. 2002), pp. 1-8, Copyright Saifun Semiconductors Ltd. 2002.
E. Maayan et al., “A 512Mb NROM Flash Data Storage Memory with 8MB/s Data Range,” ISSCC 2002 Visuals Supplement, Session 6, SRAM and Non-Volatile Memories, 6.1 and 6.2, pp. 76-77, 407-408. Copyright 1990 IEEE.
M. Janai, “Data Retention, Endurance and Acceleration Factors of NROM Devices,” IEEE 41stAnnual International Reliability Physics Symposium, Dallas, TX (2003), pp. 502-505, Copyright 1989 IEEE.
S. Minami and Y. Kamigaki, “A Novel MONOS Nonvolatile Memory Device Ensuring 10-Year Data Retention after 107Erase/Write Cycles,” IEEE Transactions on Electron Devices, vol. 40, No. 11 (Nov. 1993) pp. 2011-2017, Copyright 1998 IEEE.
C. Pan, K. Wu, P. Freiberger, A. Chatterjee, G. Sery, “A Scaling Methodology for Oxide-Nitride-Oxide Interpoly Dielectric for EPROM Applications,” IEEE Transactions on Electron Devices, vol. 37, No. 6, (Jun. 1990), pp. 1439-1443, Copyright 1990 IEEE.
P. Manos and C. Hart, “A Self-Aligned EPROM Structure with Superior Data Retention,” IEEE Electron Device Letters, vol. 11, No. 7, (Jul. 1990) pp. 309-311, Copyright 1990 IEEE.
W. Owen and W. Tchon, “E2PROM Product Issues and Technology Trends,” IEEE 1989, pp. 17-19, Copryright 1989 IEEE.
T. Huang, F. Jong, T. Chao, H. Lin, L. Leu, K. Young, C. Lin, K. Chiu, “Improving Radiation Hardness of EEPROM/Flash Cell BY N20 Annealing,” IEEE Electron Device Letters, vol. 19, No. 7 (Jul. 1998), pp. 256-258, Copyright 1998 IEEE.
B. Eitan et al., “Electrons Retention Model for Localized Charge in Oxide -Nitride-Oxide (ONO) Dielectric,” IEEE Device Lett., vol. 23, No. 9, (Sep. 2002), pp. 556-558. Copyright 2002 IEEE.
T. Nozaki, T. Tanaka, Y.Kijiya, E. Kinoshita, T. Tsuchiya, Y. Hayashi
Forbes Leonard
Prall Kirk D.
Diaz José R
Jackson, Jr. Jerome
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
LandOfFree
NROM memory cell, memory array, related devices and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with NROM memory cell, memory array, related devices and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NROM memory cell, memory array, related devices and methods will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4136406