Multiple scan chains with pin sharing

Details Multiple scan chains with pin sharing Multiple scan chains with pin sharing

2007-07-24

2007-07-24

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S814000

Reexamination Certificate

active

10136670

ABSTRACT:
A scan based design architecture reduces pin count, test time and power consumption, and also allows the use of existing verified scan vectors by driving multiple scan chains from one scan input and utilizing multiple scan clocks. The scan vectors for multiple scan chains are sequentially applied to the scan input so as to broadcast the vectors to multiple scan chains, but only the bits for one scan chain are selectively clocked into that chain by a corresponding one of the multiple scan clocks. An output multiplexer can also be used to reduce the total number of test pins. The pin count can be further reduced by using a scan clock generator to generate the multiple scan clocks from a single scan clock input, and by using a select signal generator to generate select signals that control an output multiplexer.

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