Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2002-01-16
2003-04-15
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S725000, C438S761000
Reexamination Certificate
active
06548423
ABSTRACT:
FIELD OF THE INVENTION
The present specification relates to the fabrication of integrated circuits (ICs). More specifically, the present specification relates to a hard mask process for forming integrated circuit features.
BACKGROUND OF THE INVENTION
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The radiation can be light, such as ultra-violet light, vacuum ultra-violet (VUV) light and deep ultraviolet light. The radiation can also be x-ray radiation, e-beam radiation, etc.
The lithographic photoresist coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Exposure of the lithographic coating through a photomask or reticle causes the image area to become selectively either more or less soluble (depending on the negative or positive photoresist coating) in a particular developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The photoresist material or layer associated with conventional lithographic technologies is often utilized to selectively form various IC structures, regions, and layers. Generally, the patterned photoresist material can be utilized to define doping regions, implant regions or other structures associated with an integrated circuit (IC). A conventional lithographic system is generally utilized to pattern photoresist material to form gate stacks or structures. As the features in semiconductor patterning become smaller and smaller, the photoresist thickness needed to sustain reasonable aspect ratio must decrease. A thinner photoresist may not be suitable for etch applications due to premature resist erosion. Thus, resist erosion complications facilitate the necessity for hard mask processes.
According to one conventional process, a hard mask is provided above polysilicon/oxide layers to pattern the gate stacks. The hard mask must be thin enough so that it can be etched without eroding the patterned photoresist above it. The hard mask must also be thick enough to withstand an etch process that can completely remove uncovered portions of the polysilicon layer. Accordingly, the hard mask must have a precise thickness to appropriately pattern the gate stacks.
An anti-reflective coating (ARC) has been conventionally provided underneath the photoresist material or the hard mask to reduce reflectivity and thereby, reduce resist notching, lifting and variation of critical dimension of the obtained pattern. Generally, the ARC (organic or inorganic) layer is a relatively thin layer which cannot be used as a hard mask because it is too thin and does not allow thickness flexibility due to optical design parameters.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need for a process of forming a gate stack that does not require a conventional hard mask step. Yet further, there is a need for a double ARC process. Even further still, there is a need for a gate mask process that effectively balances optical and etching efficiencies.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of fabricating an integrated circuit. The method includes providing a first anti-reflective coating layer above substrate providing a second anti-reflective coating layer above the first anti-reflective coating layer, providing a photoresist layer above the second anti-reflective coating layer. The method further includes patterning the photoresist layer and selectively etching/removing the first and the second anti-reflective coating layer in accordance with a feature defined by the photoresist layer. A first thickness of the first anti-reflective coating layer and a second thickness of the second anti-reflective coating layer are configured to reduce reflections associated with the patterning step. Also, the thickness and materials for the two layers can be chosen to be thin enough to be etched without eroding photoresist and thick enough to withstand the etching of layers underneath. The first anti-reflective layer should have substantially different resist/layer etch selectivity as compared to the second layer.
Another exemplary embodiment relates to a method of forming a gate stack for an integrated circuit. The method includes providing a first anti-reflective coating layer and a second anti-reflective coating layer over a gate conductor, providing a photoresist layer over the second anti-reflective coating layer, patterning the photoresist layer to form a first feature in the photoresist layer, and trim etching the photoresist layer to reduce size of the first feature and etching the first ARC layer to form a second feature. The method also includes etching/removing the anti-reflective coating layer in accordance with the second feature, and etching the gate conductor layer in accordance with the first anti-reflective coating layer and the second anti-reflective coating layer.
Yet another exemplary embodiment relates to a method of forming a hard mask for an integrated circuit. The method comprises steps of providing a dual layer anti-reflective coating above a substrate, providing a photoresist layer above the dual layer anti-reflective coating, patterning the photoresist layer to form a feature, trim etching the photoresist layer to reduce size of the resist feature, selectively etching the first ARC layer, removing all remaining photoresist, selectively etching the second ARC layer and the remaining stack material (polygate as an example) in accordance with the feature formed by a dual ARC layer. The patterned dual ARC layer acts as a hard mask.
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Bell Scott A.
Lukanc Todd P.
Lyons Christopher F.
Plat Marina V.
Foley & Lardner
Ghyka Alexander
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