Mode setting curcuit and method of a semiconductor memory device

Details Mode setting curcuit and method of a semiconductor memory device Mode setting curcuit and method of a semiconductor memory device

1995-07-26

1996-12-10

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365193, 36523008, G11C 700

Patent

active

055838154

ABSTRACT:
A mode setting circuit and method of a semiconductor memory device for selectively enabling a specific operation mode out of preset operation modes. The mode setting circuit gates a signal set at an internal node of a row address buffer according to a mode setting control signal. The row address buffer receives a row address signal supplied from the exterior and generates a shaped row address. The latch circuit latches a signal generated from the gating circuit and generates a mode setting signal for enabling the specific operation mode in response to a variation in a specific signal of the internal node.

REFERENCES:
patent: 4984216 (1991-01-01), Toda et al.
patent: 5301164 (1994-04-01), Miyawaki

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