Methods of forming integrated circuits containing high and low v

Details Methods of forming integrated circuits containing high and low v Methods of forming integrated circuits containing high and low v

1996-08-28

1998-11-10

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438231, 438232, H01L 218234, H01L 218236

Patent

active

058343520

ABSTRACT:
Methods of forming integrated circuits containing high and low voltage insulated-gate field effect transistors (IGFET) include the steps of forming first and second insulating layers having unequal thicknesses at first and second locations on a face of a semiconductor substrate, respectively, and then forming first and second gate electrodes on the first and second insulating layers, respectively. Formation of the source and drain regions of a high voltage IGFET is then initiated by implanting first dopants of first conductivity type through the first insulating layer and into the first location, using the first gate electrode as an implant mask. Formation of the source and drain regions (e.g., LDD) of the low voltage IGFET is then initiated by implanting second dopants of first conductivity type into the first and second insulating layers. However, the energy level of the implanted second dopants is set at a relatively low level so that the average projection range of the implanted second dopants is greater than the thickness of the second insulating layer, but less than the thickness of the first insulating layer. Thus, negligible quantities of second dopants become implanted into the already partially formed source and drain regions of the high voltage IGFET. This means that the dose level of the implanted first dopants can be preselected to meet the desired breakdown voltage characteristics of the high voltage IGFET, without contamination by the dopants used to subsequently form the low voltage IGFET.

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Philip Cacharelis et al., A 1.0 .mu.m BiCMOS With EEPROM Technology For Application In The Design Of "Smart" Analog And Mixed-Signal ASIC Products, IEEE 1992 Custom Integrated Circuits Conference, pp. 9.7.1-9.7.4 .

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