Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-10-20
1998-11-10
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438591, 438770, H01L 21336
Patent
active
058343539
ABSTRACT:
The method of the present invention includes forming a silicon oxynitride layer on a substrate. Then, a dielectric layer with high permitivity is deposited by chemical vapor deposition on the silicon oxynitride layer. Subsequently, a rapid thermal process (RTP) anneal is performed in N.sub.2 O or NO ambient to reduce the dielectric leakage. A multiple conductive layer consisting of TiN/Ti/TiN is then formed on the dielectric layer. Then, the multiple conductive layer, the dielectric layer, and the silicon oxynitride layer are patterned to form gate structure. A plasma immersion is performed to form ultra shallow extended source and drain junctions. Side wall spacers are formed on the side walls of the gate structure. Next, an ion implantation is carried out to dope ions into the substrate. Next, a rapid thermal process (RTP) anneal is performed to form shallow junctions of the source and the drain.
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Hisayo Sasaki Momose et al. "High-Frequency AC Characteristics of 1.5 nm Gate Oxide Mosfets" IEEE. 1996. pp. 105-108.
Chuan Lin et al. "Leakage Current, Reliability Characteristics, and Boron Penetration of Ultra-Thin (32-36.ANG.) 0.sub.2 -Oxides and N.sub.2 0/N0 Oxynitrides" IEEE, 1996, pp. 331-334.
S. C. Sun et al. "A Novel Approach for Leakage Current Reduction of LPCVD Ta.sub.2 0.sub.5 and Ti0.sub.2 Films by Rapid Thermal N.sub.2 0 Annealing" IEEE, 1994, pp. 333-336.
Ruth Dejule "Meeting the Ultra-Shallow Junction Challenge" Semiconductor International, Apr. 1997.
Chaudhari Chandra
Texas Instruments--Acer Incorporated
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