Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-08-16
2011-08-16
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S587000, C438S588000, C438S592000, C438S593000, C438S594000, C257SE21409
Reexamination Certificate
active
07998810
ABSTRACT:
A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.
REFERENCES:
patent: 6159797 (2000-12-01), Lee
patent: 6251729 (2001-06-01), Montree et al.
patent: 6291301 (2001-09-01), Chen
patent: 7622349 (2009-11-01), Sadd et al.
patent: 2008/0048245 (2008-02-01), Kito et al.
patent: 2008/0116503 (2008-05-01), Tsurumi et al.
patent: 2009/0001444 (2009-01-01), Matsuoka et al.
patent: 2009/0191699 (2009-07-01), Jung et al.
patent: 2003-007861 (2003-01-01), None
patent: 1020030044145 (2003-06-01), None
Choi Gil-heyun
Jung Eun-Ji
Kim Byung-hee
Lee Chang-Won
Lee Jeong-gil
Garber Charles D
Myers Bigel & Sibley & Sajovec
Roman Angel
Samsung Electronics Co,. Ltd.
LandOfFree
Methods of forming integrated circuit devices having stacked... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming integrated circuit devices having stacked..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming integrated circuit devices having stacked... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2762724