Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-10-16
2007-10-16
Tran, Binh X. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S700000, C438S720000, C438S736000
Reexamination Certificate
active
11216686
ABSTRACT:
Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.
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Hong Duk Ho
Knoefler Roman
Lee Kyoung Woo
Naujok Markus
Infineon - Technologies AG
Myers Bigel & Sibley Sajovec, PA
Samsung Electronics Co,. Ltd.
Tran Binh X.
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