Methods of fabricating flash memory devices comprising...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S587000, C257S316000, C257SE21129, C257SE21422

Reexamination Certificate

active

08043914

ABSTRACT:
Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

REFERENCES:
patent: 2004/0121590 (2004-06-01), Moon et al.
patent: 2004/0157453 (2004-08-01), Delgadino et al.
patent: 2006/0289938 (2006-12-01), Kim
patent: 2007/0034929 (2007-02-01), Hwang et al.
patent: 2007/0057316 (2007-03-01), Yaegashi
patent: 2008/0003745 (2008-01-01), Myung et al.
patent: 2008/0057736 (2008-03-01), Lee
patent: 2010/0210099 (2010-08-01), Hur et al.
patent: 2007-073887 (2007-03-01), None
patent: 1020080003171 (2008-01-01), None
patent: 1020080006897 (2008-01-01), None

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